510   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
516   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
543   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
599   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
608   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
649   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
753   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
756   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
806   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
832   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
835   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
885   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
911   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
914   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
964   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
990   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
993   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1031   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1054   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1062   MODIFY_REG(TIMx->CCER,  in IC1Config()
1087   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1095   MODIFY_REG(TIMx->CCER,  in IC2Config()
1120   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1128   MODIFY_REG(TIMx->CCER,  in IC3Config()
1153   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1161   MODIFY_REG(TIMx->CCER,  in IC4Config()