Lines Matching refs:Timing
399 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
407 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
408 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
409 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
410 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
411 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
412 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
413 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
417 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
418 … ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
419 … ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) | in FMC_NORSRAM_Timing_Init()
420 … ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) | in FMC_NORSRAM_Timing_Init()
421 … (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) | in FMC_NORSRAM_Timing_Init()
422 … (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) | in FMC_NORSRAM_Timing_Init()
423 (Timing->AccessMode))); in FMC_NORSRAM_Timing_Init()
430 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
451 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FMC_NORSRAM_Extended_Timing_Init() argument
462 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
463 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
464 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
465 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Extended_Timing_Init()
466 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Extended_Timing_Init()
470 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
471 … ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
472 … ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
473 … Timing->AccessMode | in FMC_NORSRAM_Extended_Timing_Init()
474 … ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos))); in FMC_NORSRAM_Extended_Timing_Init()
657 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_CommonSpace_Timing_Init() argument
661 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
662 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
663 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
664 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
672 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_CommonSpace_Timing_Init()
673 … ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
674 … ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
675 … ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); in FMC_NAND_CommonSpace_Timing_Init()
680 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_CommonSpace_Timing_Init()
681 … ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
682 … ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
683 … ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); in FMC_NAND_CommonSpace_Timing_Init()
690 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
691 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
692 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
693 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos))); in FMC_NAND_CommonSpace_Timing_Init()
708 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_AttributeSpace_Timing_Init() argument
712 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
713 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
714 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
715 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
723 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_AttributeSpace_Timing_Init()
724 … ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
725 … ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
726 … ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); in FMC_NAND_AttributeSpace_Timing_Init()
731 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_AttributeSpace_Timing_Init()
732 … ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
733 … ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
734 … ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); in FMC_NAND_AttributeSpace_Timing_Init()
741 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
742 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
743 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
744 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos))); in FMC_NAND_AttributeSpace_Timing_Init()
1026 FMC_NAND_PCC_TimingTypeDef *Timing) in FMC_PCCARD_CommonSpace_Timing_Init() argument
1031 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_PCCARD_CommonSpace_Timing_Init()
1032 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_PCCARD_CommonSpace_Timing_Init()
1033 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_PCCARD_CommonSpace_Timing_Init()
1034 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_PCCARD_CommonSpace_Timing_Init()
1039 (Timing->SetupTime | in FMC_PCCARD_CommonSpace_Timing_Init()
1040 ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) | in FMC_PCCARD_CommonSpace_Timing_Init()
1041 ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) | in FMC_PCCARD_CommonSpace_Timing_Init()
1042 ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos))); in FMC_PCCARD_CommonSpace_Timing_Init()
1055 FMC_NAND_PCC_TimingTypeDef *Timing) in FMC_PCCARD_AttributeSpace_Timing_Init() argument
1060 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_PCCARD_AttributeSpace_Timing_Init()
1061 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_PCCARD_AttributeSpace_Timing_Init()
1062 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_PCCARD_AttributeSpace_Timing_Init()
1063 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_PCCARD_AttributeSpace_Timing_Init()
1068 (Timing->SetupTime | in FMC_PCCARD_AttributeSpace_Timing_Init()
1069 ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) | in FMC_PCCARD_AttributeSpace_Timing_Init()
1070 ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) | in FMC_PCCARD_AttributeSpace_Timing_Init()
1071 ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos))); in FMC_PCCARD_AttributeSpace_Timing_Init()
1084 FMC_NAND_PCC_TimingTypeDef *Timing) in FMC_PCCARD_IOSpace_Timing_Init() argument
1089 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_PCCARD_IOSpace_Timing_Init()
1090 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_PCCARD_IOSpace_Timing_Init()
1091 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_PCCARD_IOSpace_Timing_Init()
1092 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_PCCARD_IOSpace_Timing_Init()
1097 (Timing->SetupTime | in FMC_PCCARD_IOSpace_Timing_Init()
1098 (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) | in FMC_PCCARD_IOSpace_Timing_Init()
1099 (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) | in FMC_PCCARD_IOSpace_Timing_Init()
1100 (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos))); in FMC_PCCARD_IOSpace_Timing_Init()
1244 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_SDRAM_Timing_Init() argument
1248 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); in FMC_SDRAM_Timing_Init()
1249 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); in FMC_SDRAM_Timing_Init()
1250 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); in FMC_SDRAM_Timing_Init()
1251 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); in FMC_SDRAM_Timing_Init()
1252 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); in FMC_SDRAM_Timing_Init()
1253 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); in FMC_SDRAM_Timing_Init()
1254 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); in FMC_SDRAM_Timing_Init()
1262 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
1263 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
1264 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
1265 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | in FMC_SDRAM_Timing_Init()
1266 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
1267 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | in FMC_SDRAM_Timing_Init()
1268 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
1275 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | in FMC_SDRAM_Timing_Init()
1276 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); in FMC_SDRAM_Timing_Init()
1280 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
1281 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
1282 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
1283 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
1284 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()