Lines Matching refs:Init

240                                     FMC_NORSRAM_InitTypeDef *Init)  in FMC_NORSRAM_Init()  argument
248 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
249 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
250 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
251 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
252 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
253 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
255 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); in FMC_NORSRAM_Init()
257 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
258 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
259 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
260 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); in FMC_NORSRAM_Init()
261 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); in FMC_NORSRAM_Init()
262 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); in FMC_NORSRAM_Init()
264 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); in FMC_NORSRAM_Init()
267 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); in FMC_NORSRAM_Init()
269 assert_param(IS_FMC_PAGESIZE(Init->PageSize)); in FMC_NORSRAM_Init()
272 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
275 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) in FMC_NORSRAM_Init()
285 Init->DataAddressMux | \ in FMC_NORSRAM_Init()
286 Init->MemoryType | \ in FMC_NORSRAM_Init()
287 Init->MemoryDataWidth | \ in FMC_NORSRAM_Init()
288 Init->BurstAccessMode | \ in FMC_NORSRAM_Init()
289 Init->WaitSignalPolarity | \ in FMC_NORSRAM_Init()
290 Init->WaitSignalActive | \ in FMC_NORSRAM_Init()
291 Init->WriteOperation | \ in FMC_NORSRAM_Init()
292 Init->WaitSignal | \ in FMC_NORSRAM_Init()
293 Init->ExtendedMode | \ in FMC_NORSRAM_Init()
294 Init->AsynchronousWait | \ in FMC_NORSRAM_Init()
295 Init->WriteBurst); in FMC_NORSRAM_Init()
298 btcr_reg |= Init->WrapMode; in FMC_NORSRAM_Init()
301 btcr_reg |= Init->ContinuousClock; in FMC_NORSRAM_Init()
304 btcr_reg |= Init->WriteFifo; in FMC_NORSRAM_Init()
306 btcr_reg |= Init->PageSize; in FMC_NORSRAM_Init()
333 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
337 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
339 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
344 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
347 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
598 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
602 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); in FMC_NAND_Init()
603 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); in FMC_NAND_Init()
604 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NAND_Init()
605 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); in FMC_NAND_Init()
606 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); in FMC_NAND_Init()
607 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); in FMC_NAND_Init()
608 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); in FMC_NAND_Init()
612 if (Init->NandBank == FMC_NAND_BANK2) in FMC_NAND_Init()
615 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
617Init->MemoryDataWidth | in FMC_NAND_Init()
618Init->EccComputation | in FMC_NAND_Init()
619Init->ECCPageSize | in FMC_NAND_Init()
620 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | in FMC_NAND_Init()
621 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); in FMC_NAND_Init()
626 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
628Init->MemoryDataWidth | in FMC_NAND_Init()
629Init->EccComputation | in FMC_NAND_Init()
630Init->ECCPageSize | in FMC_NAND_Init()
631 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | in FMC_NAND_Init()
632 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); in FMC_NAND_Init()
636 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
638 Init->MemoryDataWidth | in FMC_NAND_Init()
639 Init->EccComputation | in FMC_NAND_Init()
640 Init->ECCPageSize | in FMC_NAND_Init()
641 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | in FMC_NAND_Init()
642 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); in FMC_NAND_Init()
992 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) in FMC_PCCARD_Init() argument
997 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); in FMC_PCCARD_Init()
998 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); in FMC_PCCARD_Init()
999 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); in FMC_PCCARD_Init()
1010 Init->Waitfeature | in FMC_PCCARD_Init()
1012 (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) | in FMC_PCCARD_Init()
1013 (Init->TARSetupTime << FMC_PCR4_TAR_Pos))); in FMC_PCCARD_Init()
1181 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
1185 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); in FMC_SDRAM_Init()
1186 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); in FMC_SDRAM_Init()
1187 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); in FMC_SDRAM_Init()
1188 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_SDRAM_Init()
1189 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); in FMC_SDRAM_Init()
1190 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); in FMC_SDRAM_Init()
1191 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); in FMC_SDRAM_Init()
1192 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); in FMC_SDRAM_Init()
1193 assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); in FMC_SDRAM_Init()
1194 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); in FMC_SDRAM_Init()
1197 if (Init->SDBank == FMC_SDRAM_BANK1) in FMC_SDRAM_Init()
1201 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
1202 Init->RowBitsNumber | in FMC_SDRAM_Init()
1203 Init->MemoryDataWidth | in FMC_SDRAM_Init()
1204 Init->InternalBankNumber | in FMC_SDRAM_Init()
1205 Init->CASLatency | in FMC_SDRAM_Init()
1206 Init->WriteProtection | in FMC_SDRAM_Init()
1207 Init->SDClockPeriod | in FMC_SDRAM_Init()
1208 Init->ReadBurst | in FMC_SDRAM_Init()
1209 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
1217 (Init->SDClockPeriod | in FMC_SDRAM_Init()
1218 Init->ReadBurst | in FMC_SDRAM_Init()
1219 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
1223 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
1224 Init->RowBitsNumber | in FMC_SDRAM_Init()
1225 Init->MemoryDataWidth | in FMC_SDRAM_Init()
1226 Init->InternalBankNumber | in FMC_SDRAM_Init()
1227 Init->CASLatency | in FMC_SDRAM_Init()
1228 Init->WriteProtection)); in FMC_SDRAM_Init()