Lines Matching refs:Device
239 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
247 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
272 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
333 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
339 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
347 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
361 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
365 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
370 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
376 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
381 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
384 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
398 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Timing_Init() argument
406 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Timing_Init()
417 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
427 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
429 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
431 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
450 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, in FMC_NORSRAM_Extended_Timing_Init() argument
461 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); in FMC_NORSRAM_Extended_Timing_Init()
470 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
478 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
508 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Enable() argument
511 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Enable()
515 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
526 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Disable() argument
529 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Disable()
533 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Disable()
598 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
601 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_Init()
615 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
626 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
636 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
656 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_CommonSpace_Timing_Init() argument
660 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_CommonSpace_Timing_Init()
672 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_CommonSpace_Timing_Init()
680 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_CommonSpace_Timing_Init()
690 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
707 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_AttributeSpace_Timing_Init() argument
711 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_AttributeSpace_Timing_Init()
723 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_AttributeSpace_Timing_Init()
731 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_AttributeSpace_Timing_Init()
741 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
756 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_DeInit() argument
759 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_DeInit()
763 __FMC_NAND_DISABLE(Device, Bank); in FMC_NAND_DeInit()
770 WRITE_REG(Device->PCR2, 0x00000018U); in FMC_NAND_DeInit()
771 WRITE_REG(Device->SR2, 0x00000040U); in FMC_NAND_DeInit()
772 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); in FMC_NAND_DeInit()
773 WRITE_REG(Device->PATT2, 0xFCFCFCFCU); in FMC_NAND_DeInit()
779 WRITE_REG(Device->PCR3, 0x00000018U); in FMC_NAND_DeInit()
780 WRITE_REG(Device->SR3, 0x00000040U); in FMC_NAND_DeInit()
781 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); in FMC_NAND_DeInit()
782 WRITE_REG(Device->PATT3, 0xFCFCFCFCU); in FMC_NAND_DeInit()
789 WRITE_REG(Device->PCR, 0x00000018U); in FMC_NAND_DeInit()
790 WRITE_REG(Device->SR, 0x00000040U); in FMC_NAND_DeInit()
791 WRITE_REG(Device->PMEM, 0xFCFCFCFCU); in FMC_NAND_DeInit()
792 WRITE_REG(Device->PATT, 0xFCFCFCFCU); in FMC_NAND_DeInit()
824 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Enable() argument
827 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Enable()
834 SET_BIT(Device->PCR2, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Enable()
838 SET_BIT(Device->PCR3, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Enable()
844 SET_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Enable()
857 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Disable() argument
860 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Disable()
867 CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Disable()
871 CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Disable()
877 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Disable()
891 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, in FMC_NAND_GetECC() argument
897 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_GetECC()
904 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) in FMC_NAND_GetECC()
920 *ECCval = (uint32_t)Device->ECCR2; in FMC_NAND_GetECC()
925 *ECCval = (uint32_t)Device->ECCR3; in FMC_NAND_GetECC()
932 *ECCval = (uint32_t)Device->ECCR; in FMC_NAND_GetECC()
992 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) in FMC_PCCARD_Init() argument
995 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_Init()
1003 MODIFY_REG(Device->PCR4, in FMC_PCCARD_Init()
1025 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, in FMC_PCCARD_CommonSpace_Timing_Init() argument
1029 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_CommonSpace_Timing_Init()
1038 MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK, in FMC_PCCARD_CommonSpace_Timing_Init()
1054 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, in FMC_PCCARD_AttributeSpace_Timing_Init() argument
1058 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_AttributeSpace_Timing_Init()
1067 MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK, in FMC_PCCARD_AttributeSpace_Timing_Init()
1083 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, in FMC_PCCARD_IOSpace_Timing_Init() argument
1087 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_IOSpace_Timing_Init()
1096 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, in FMC_PCCARD_IOSpace_Timing_Init()
1110 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) in FMC_PCCARD_DeInit() argument
1113 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_DeInit()
1116 __FMC_PCCARD_DISABLE(Device); in FMC_PCCARD_DeInit()
1119 Device->PCR4 = 0x00000018U; in FMC_PCCARD_DeInit()
1120 Device->SR4 = 0x00000040U; in FMC_PCCARD_DeInit()
1121 Device->PMEM4 = 0xFCFCFCFCU; in FMC_PCCARD_DeInit()
1122 Device->PATT4 = 0xFCFCFCFCU; in FMC_PCCARD_DeInit()
1123 Device->PIO4 = 0xFCFCFCFCU; in FMC_PCCARD_DeInit()
1181 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
1184 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Init()
1199 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
1213 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
1221 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
1243 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_Timing_Init() argument
1247 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Timing_Init()
1260 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
1272 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
1278 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
1295 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_DeInit() argument
1298 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_DeInit()
1302 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
1303 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
1304 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
1305 Device->SDRTR = 0x00000000U; in FMC_SDRAM_DeInit()
1306 Device->SDSR = 0x00000000U; in FMC_SDRAM_DeInit()
1336 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Enable() argument
1339 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Enable()
1343 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
1353 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Disable() argument
1356 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Disable()
1360 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
1373 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SendCommand() argument
1378 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SendCommand()
1385 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1393 while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) in FMC_SDRAM_SendCommand()
1413 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) in FMC_SDRAM_ProgramRefreshRate() argument
1416 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_ProgramRefreshRate()
1420 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); in FMC_SDRAM_ProgramRefreshRate()
1431 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SetAutoRefreshNumber() argument
1435 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SetAutoRefreshNumber()
1439 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
1453 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_GetModeStatus() argument
1458 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_GetModeStatus()
1464 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); in FMC_SDRAM_GetModeStatus()
1468 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); in FMC_SDRAM_GetModeStatus()