Lines Matching refs:hqspi
260 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, F…
261 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_…
262 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod…
292 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Init() argument
298 if(hqspi == NULL) in HAL_QSPI_Init()
304 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance)); in HAL_QSPI_Init()
305 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); in HAL_QSPI_Init()
306 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
307 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
308 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); in HAL_QSPI_Init()
309 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); in HAL_QSPI_Init()
310 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); in HAL_QSPI_Init()
311 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); in HAL_QSPI_Init()
313 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) in HAL_QSPI_Init()
315 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); in HAL_QSPI_Init()
318 if(hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_Init()
321 hqspi->Lock = HAL_UNLOCKED; in HAL_QSPI_Init()
325 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_Init()
326 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_Init()
327 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_Init()
328 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_Init()
329 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_Init()
330 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_Init()
331 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_Init()
332 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_Init()
333 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_Init()
334 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_Init()
336 if(hqspi->MspInitCallback == NULL) in HAL_QSPI_Init()
338 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_Init()
342 hqspi->MspInitCallback(hqspi); in HAL_QSPI_Init()
345 HAL_QSPI_MspInit(hqspi); in HAL_QSPI_Init()
349 HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); in HAL_QSPI_Init()
353 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_Init()
354 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
357 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Init()
362 …MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUAD… in HAL_QSPI_Init()
363 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | in HAL_QSPI_Init()
364 hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); in HAL_QSPI_Init()
367 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), in HAL_QSPI_Init()
368 ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | in HAL_QSPI_Init()
369 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); in HAL_QSPI_Init()
372 __HAL_QSPI_ENABLE(hqspi); in HAL_QSPI_Init()
375 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Init()
378 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Init()
382 __HAL_UNLOCK(hqspi); in HAL_QSPI_Init()
393 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_DeInit() argument
396 if(hqspi == NULL) in HAL_QSPI_DeInit()
402 __HAL_QSPI_DISABLE(hqspi); in HAL_QSPI_DeInit()
405 if(hqspi->MspDeInitCallback == NULL) in HAL_QSPI_DeInit()
407 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_DeInit()
411 hqspi->MspDeInitCallback(hqspi); in HAL_QSPI_DeInit()
414 HAL_QSPI_MspDeInit(hqspi); in HAL_QSPI_DeInit()
418 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_DeInit()
421 hqspi->State = HAL_QSPI_STATE_RESET; in HAL_QSPI_DeInit()
424 __HAL_UNLOCK(hqspi); in HAL_QSPI_DeInit()
434 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspInit() argument
437 UNUSED(hqspi); in HAL_QSPI_MspInit()
449 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspDeInit() argument
452 UNUSED(hqspi); in HAL_QSPI_MspDeInit()
488 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_IRQHandler() argument
491 uint32_t flag = READ_REG(hqspi->Instance->SR); in HAL_QSPI_IRQHandler()
492 uint32_t itsource = READ_REG(hqspi->Instance->CR); in HAL_QSPI_IRQHandler()
497 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
499 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
502 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
504 if (hqspi->TxXferCount > 0U) in HAL_QSPI_IRQHandler()
507 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_IRQHandler()
508 hqspi->pTxBuffPtr++; in HAL_QSPI_IRQHandler()
509 hqspi->TxXferCount--; in HAL_QSPI_IRQHandler()
515 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
520 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
523 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
525 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
528 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
529 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
530 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
536 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
548 hqspi->FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
550 HAL_QSPI_FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
558 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); in HAL_QSPI_IRQHandler()
561 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
564 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
566 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
569 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
572 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
576 HAL_QSPI_Abort_IT(hqspi); in HAL_QSPI_IRQHandler()
579 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
583 hqspi->TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
585 HAL_QSPI_TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
588 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
590 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
593 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
596 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
600 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
601 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) in HAL_QSPI_IRQHandler()
603 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
606 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
607 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
608 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
619 HAL_QSPI_Abort_IT(hqspi); in HAL_QSPI_IRQHandler()
622 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
626 hqspi->RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
628 HAL_QSPI_RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
631 else if(hqspi->State == HAL_QSPI_STATE_BUSY) in HAL_QSPI_IRQHandler()
634 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
638 hqspi->CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
640 HAL_QSPI_CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
643 else if(hqspi->State == HAL_QSPI_STATE_ABORT) in HAL_QSPI_IRQHandler()
646 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_IRQHandler()
649 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
651 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) in HAL_QSPI_IRQHandler()
657 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
659 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
668 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
670 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
684 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); in HAL_QSPI_IRQHandler()
687 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) in HAL_QSPI_IRQHandler()
690 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_IRQHandler()
693 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
698 hqspi->StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
700 HAL_QSPI_StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
708 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); in HAL_QSPI_IRQHandler()
711 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
714 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; in HAL_QSPI_IRQHandler()
716 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
719 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
722 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_IRQHandler()
723 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_IRQHandler()
726 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_IRQHandler()
729 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
733 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
735 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
742 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
746 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
748 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
757 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); in HAL_QSPI_IRQHandler()
761 hqspi->TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
763 HAL_QSPI_TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
781 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Ti… in HAL_QSPI_Command() argument
813 __HAL_LOCK(hqspi); in HAL_QSPI_Command()
815 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command()
817 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command()
820 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command()
823 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_Command()
828 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command()
834 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Command()
838 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Command()
841 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
847 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
857 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command()
870 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) in HAL_QSPI_Command_IT() argument
901 __HAL_LOCK(hqspi); in HAL_QSPI_Command_IT()
903 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command_IT()
905 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command_IT()
908 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command_IT()
911 status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); in HAL_QSPI_Command_IT()
918 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Command_IT()
922 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command_IT()
929 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
932 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); in HAL_QSPI_Command_IT()
937 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command_IT()
940 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
946 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
954 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
969 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Transmit() argument
973 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Transmit()
976 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit()
978 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit()
980 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit()
985 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit()
988 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
989 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
990 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit()
993 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
995 while(hqspi->TxXferCount > 0U) in HAL_QSPI_Transmit()
998 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1005 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_Transmit()
1006 hqspi->pTxBuffPtr++; in HAL_QSPI_Transmit()
1007 hqspi->TxXferCount--; in HAL_QSPI_Transmit()
1013 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1018 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Transmit()
1021 status = HAL_QSPI_Abort(hqspi); in HAL_QSPI_Transmit()
1026 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit()
1030 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit()
1040 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit()
1054 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Receive() argument
1058 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive()
1059 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Receive()
1062 __HAL_LOCK(hqspi); in HAL_QSPI_Receive()
1064 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive()
1066 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive()
1071 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive()
1074 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1075 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1076 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive()
1079 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
1082 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
1084 while(hqspi->RxXferCount > 0U) in HAL_QSPI_Receive()
1087 …status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Time… in HAL_QSPI_Receive()
1094 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_Receive()
1095 hqspi->pRxBuffPtr++; in HAL_QSPI_Receive()
1096 hqspi->RxXferCount--; in HAL_QSPI_Receive()
1102 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Receive()
1107 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Receive()
1110 status = HAL_QSPI_Abort(hqspi); in HAL_QSPI_Receive()
1115 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive()
1119 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive()
1129 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive()
1141 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_IT() argument
1146 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_IT()
1148 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_IT()
1150 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_IT()
1155 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_IT()
1158 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1159 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1160 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_IT()
1163 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Transmit_IT()
1166 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
1169 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1172 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Transmit_IT()
1176 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_IT()
1180 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1188 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1201 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_IT() argument
1204 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_IT()
1207 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_IT()
1209 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_IT()
1211 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_IT()
1216 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_IT()
1219 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1220 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1221 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_IT()
1224 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Receive_IT()
1227 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
1230 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1233 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1236 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Receive_IT()
1240 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_IT()
1244 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1252 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1269 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_DMA() argument
1272 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Transmit_DMA()
1275 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1277 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_DMA()
1280 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_DMA()
1285 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Transmit_DMA()
1287 hqspi->TxXferCount = data_size; in HAL_QSPI_Transmit_DMA()
1289 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Transmit_DMA()
1291 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1295 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1299 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1303 hqspi->TxXferCount = (data_size >> 1U); in HAL_QSPI_Transmit_DMA()
1306 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Transmit_DMA()
1308 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1312 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1316 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1320 hqspi->TxXferCount = (data_size >> 2U); in HAL_QSPI_Transmit_DMA()
1331 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_DMA()
1334 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Transmit_DMA()
1337 hqspi->TxXferSize = hqspi->TxXferCount; in HAL_QSPI_Transmit_DMA()
1338 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_DMA()
1341 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1344 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; in HAL_QSPI_Transmit_DMA()
1347 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; in HAL_QSPI_Transmit_DMA()
1350 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Transmit_DMA()
1353 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Transmit_DMA()
1364 hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE; in HAL_QSPI_Transmit_DMA()
1367 hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE; in HAL_QSPI_Transmit_DMA()
1370 …MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc |… in HAL_QSPI_Transmit_DMA()
1373 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; in HAL_QSPI_Transmit_DMA()
1376 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; in HAL_QSPI_Transmit_DMA()
1380 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Transmit_DMA()
1383 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSi… in HAL_QSPI_Transmit_DMA()
1386 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1389 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Transmit_DMA()
1392 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Transmit_DMA()
1397 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Transmit_DMA()
1398 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit_DMA()
1401 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1407 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1411 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1419 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1436 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_DMA() argument
1439 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_DMA()
1440 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Receive_DMA()
1443 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_DMA()
1445 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_DMA()
1448 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_DMA()
1453 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Receive_DMA()
1455 hqspi->RxXferCount = data_size; in HAL_QSPI_Receive_DMA()
1457 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Receive_DMA()
1459 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1463 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1467 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1471 hqspi->RxXferCount = (data_size >> 1U); in HAL_QSPI_Receive_DMA()
1474 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Receive_DMA()
1476 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
1480 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1484 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1488 hqspi->RxXferCount = (data_size >> 2U); in HAL_QSPI_Receive_DMA()
1499 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_DMA()
1502 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Receive_DMA()
1505 hqspi->RxXferSize = hqspi->RxXferCount; in HAL_QSPI_Receive_DMA()
1506 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_DMA()
1509 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; in HAL_QSPI_Receive_DMA()
1512 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; in HAL_QSPI_Receive_DMA()
1515 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Receive_DMA()
1518 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Receive_DMA()
1531 hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE; in HAL_QSPI_Receive_DMA()
1534 hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE; in HAL_QSPI_Receive_DMA()
1537 …MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc |… in HAL_QSPI_Receive_DMA()
1540 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; in HAL_QSPI_Receive_DMA()
1544 WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U)); in HAL_QSPI_Receive_DMA()
1547 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Receive_DMA()
1550 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1553 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1556 …if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSiz… in HAL_QSPI_Receive_DMA()
1559 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Receive_DMA()
1562 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1565 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Receive_DMA()
1570 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1571 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive_DMA()
1574 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1578 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; in HAL_QSPI_Receive_DMA()
1581 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Receive_DMA()
1584 …if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSiz… in HAL_QSPI_Receive_DMA()
1587 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1590 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1593 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1596 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Receive_DMA()
1599 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Receive_DMA()
1604 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1605 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive_DMA()
1608 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1615 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1619 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1627 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1642 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_Au… in HAL_QSPI_AutoPolling() argument
1678 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling()
1680 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling()
1682 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling()
1685 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling()
1688 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1693 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1696 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1699 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
1703 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling()
1708 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling()
1711 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1715 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); in HAL_QSPI_AutoPolling()
1718 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_AutoPolling()
1728 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling()
1742 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI… in HAL_QSPI_AutoPolling_IT() argument
1778 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1780 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling_IT()
1782 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling_IT()
1785 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling_IT()
1788 status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); in HAL_QSPI_AutoPolling_IT()
1793 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling_IT()
1796 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling_IT()
1799 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling_IT()
1802 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling_IT()
1806 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); in HAL_QSPI_AutoPolling_IT()
1810 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling_IT()
1813 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1816 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_AutoPolling_IT()
1822 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1830 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1845 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_M… in HAL_QSPI_MemoryMapped() argument
1879 __HAL_LOCK(hqspi); in HAL_QSPI_MemoryMapped()
1881 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_MemoryMapped()
1883 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_MemoryMapped()
1886 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; in HAL_QSPI_MemoryMapped()
1889 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_MemoryMapped()
1894 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); in HAL_QSPI_MemoryMapped()
1901 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); in HAL_QSPI_MemoryMapped()
1904 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); in HAL_QSPI_MemoryMapped()
1907 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); in HAL_QSPI_MemoryMapped()
1911 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); in HAL_QSPI_MemoryMapped()
1920 __HAL_UNLOCK(hqspi); in HAL_QSPI_MemoryMapped()
1931 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_ErrorCallback() argument
1934 UNUSED(hqspi); in HAL_QSPI_ErrorCallback()
1946 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_AbortCpltCallback() argument
1949 UNUSED(hqspi); in HAL_QSPI_AbortCpltCallback()
1961 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_CmdCpltCallback() argument
1964 UNUSED(hqspi); in HAL_QSPI_CmdCpltCallback()
1976 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxCpltCallback() argument
1979 UNUSED(hqspi); in HAL_QSPI_RxCpltCallback()
1991 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxCpltCallback() argument
1994 UNUSED(hqspi); in HAL_QSPI_TxCpltCallback()
2006 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxHalfCpltCallback() argument
2009 UNUSED(hqspi); in HAL_QSPI_RxHalfCpltCallback()
2021 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxHalfCpltCallback() argument
2024 UNUSED(hqspi); in HAL_QSPI_TxHalfCpltCallback()
2036 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_FifoThresholdCallback() argument
2039 UNUSED(hqspi); in HAL_QSPI_FifoThresholdCallback()
2051 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_StatusMatchCallback() argument
2054 UNUSED(hqspi); in HAL_QSPI_StatusMatchCallback()
2066 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TimeOutCallback() argument
2069 UNUSED(hqspi); in HAL_QSPI_TimeOutCallback()
2097 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef … in HAL_QSPI_RegisterCallback() argument
2104 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2109 __HAL_LOCK(hqspi); in HAL_QSPI_RegisterCallback()
2111 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_RegisterCallback()
2116 hqspi->ErrorCallback = pCallback; in HAL_QSPI_RegisterCallback()
2119 hqspi->AbortCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2122 hqspi->FifoThresholdCallback = pCallback; in HAL_QSPI_RegisterCallback()
2125 hqspi->CmdCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2128 hqspi->RxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2131 hqspi->TxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2134 hqspi->RxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2137 hqspi->TxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2140 hqspi->StatusMatchCallback = pCallback; in HAL_QSPI_RegisterCallback()
2143 hqspi->TimeOutCallback = pCallback; in HAL_QSPI_RegisterCallback()
2146 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2149 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2153 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2159 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_RegisterCallback()
2164 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2167 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2171 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2180 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2186 __HAL_UNLOCK(hqspi); in HAL_QSPI_RegisterCallback()
2210 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDe… in HAL_QSPI_UnRegisterCallback() argument
2215 __HAL_LOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2217 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_UnRegisterCallback()
2222 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_UnRegisterCallback()
2225 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_UnRegisterCallback()
2228 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_UnRegisterCallback()
2231 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_UnRegisterCallback()
2234 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2237 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2240 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2243 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2246 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_UnRegisterCallback()
2249 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_UnRegisterCallback()
2252 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2255 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2259 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2265 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_UnRegisterCallback()
2270 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2273 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2277 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2286 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2292 __HAL_UNLOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2324 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetState() argument
2327 return hqspi->State; in HAL_QSPI_GetState()
2335 uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetError() argument
2337 return hqspi->ErrorCode; in HAL_QSPI_GetError()
2345 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort() argument
2351 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort()
2354 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort()
2356 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort()
2359 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort()
2362 status = HAL_DMA_Abort(hqspi->hdma); in HAL_QSPI_Abort()
2365 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Abort()
2369 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort()
2372 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort()
2375 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2379 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort()
2382 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2388 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_Abort()
2391 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2397 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2409 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort_IT() argument
2414 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort_IT()
2417 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort_IT()
2420 hqspi->State = HAL_QSPI_STATE_ABORT; in HAL_QSPI_Abort_IT()
2423 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); in HAL_QSPI_Abort_IT()
2425 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort_IT()
2428 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort_IT()
2431 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_Abort_IT()
2432 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_Abort_IT()
2435 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2439 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2441 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2447 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort_IT()
2450 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort_IT()
2453 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in HAL_QSPI_Abort_IT()
2456 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort_IT()
2461 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2473 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) in HAL_QSPI_SetTimeout() argument
2475 hqspi->Timeout = Timeout; in HAL_QSPI_SetTimeout()
2483 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) in HAL_QSPI_SetFifoThreshold() argument
2488 __HAL_LOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2490 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFifoThreshold()
2493 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2496 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_SetFifoThreshold()
2497 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
2505 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2515 uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetFifoThreshold() argument
2517 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); in HAL_QSPI_GetFifoThreshold()
2527 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) in HAL_QSPI_SetFlashID() argument
2535 __HAL_LOCK(hqspi); in HAL_QSPI_SetFlashID()
2537 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFlashID()
2540 hqspi->Init.FlashID = FlashID; in HAL_QSPI_SetFlashID()
2543 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); in HAL_QSPI_SetFlashID()
2551 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFlashID()
2576 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxCplt() local
2577 hqspi->RxXferCount = 0U; in QSPI_DMARxCplt()
2580 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMARxCplt()
2590 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxCplt() local
2591 hqspi->TxXferCount = 0U; in QSPI_DMATxCplt()
2594 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMATxCplt()
2604 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxHalfCplt() local
2607 hqspi->RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2609 HAL_QSPI_RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2620 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxHalfCplt() local
2623 hqspi->TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2625 HAL_QSPI_TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2636 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAError() local
2641 hqspi->RxXferCount = 0U; in QSPI_DMAError()
2642 hqspi->TxXferCount = 0U; in QSPI_DMAError()
2643 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in QSPI_DMAError()
2646 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in QSPI_DMAError()
2649 (void)HAL_QSPI_Abort_IT(hqspi); in QSPI_DMAError()
2661 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAAbortCplt() local
2663 hqspi->RxXferCount = 0U; in QSPI_DMAAbortCplt()
2664 hqspi->TxXferCount = 0U; in QSPI_DMAAbortCplt()
2666 if(hqspi->State == HAL_QSPI_STATE_ABORT) in QSPI_DMAAbortCplt()
2670 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in QSPI_DMAAbortCplt()
2673 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMAAbortCplt()
2676 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in QSPI_DMAAbortCplt()
2682 hqspi->State = HAL_QSPI_STATE_READY; in QSPI_DMAAbortCplt()
2686 hqspi->ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2688 HAL_QSPI_ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2702 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, in QSPI_WaitFlagStateUntilTimeout() argument
2706 while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) in QSPI_WaitFlagStateUntilTimeout()
2713 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout()
2714 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout()
2731 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_… in QSPI_WaitFlagStateUntilTimeout_CPUCycle() argument
2738 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout_CPUCycle()
2739 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout_CPUCycle()
2743 while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State); in QSPI_WaitFlagStateUntilTimeout_CPUCycle()
2760 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod… in QSPI_Config() argument
2767 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); in QSPI_Config()
2775 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2781 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2790 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2797 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2804 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2813 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2821 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2828 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2834 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2843 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2849 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2858 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2865 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2871 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2880 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2888 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2897 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2903 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()