Lines Matching refs:tmpreg1
710 uint32_t tmpreg1; in HAL_ETH_Start() local
727 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Start()
729 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Start()
736 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Start()
738 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Start()
767 uint32_t tmpreg1; in HAL_ETH_Start_IT() local
784 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Start_IT()
786 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Start_IT()
803 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Start_IT()
805 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Start_IT()
835 uint32_t tmpreg1; in HAL_ETH_Stop() local
853 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Stop()
855 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Stop()
865 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Stop()
867 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Stop()
890 uint32_t tmpreg1; in HAL_ETH_Stop_IT() local
912 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Stop_IT()
914 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Stop_IT()
924 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_Stop_IT()
926 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_Stop_IT()
2084 uint32_t tmpreg1; in HAL_ETH_ReadPHYRegister() local
2088 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_ReadPHYRegister()
2091 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; in HAL_ETH_ReadPHYRegister()
2094 …tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device addr… in HAL_ETH_ReadPHYRegister()
2095 …tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register ad… in HAL_ETH_ReadPHYRegister()
2096 …tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode … in HAL_ETH_ReadPHYRegister()
2097 …tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit … in HAL_ETH_ReadPHYRegister()
2100 heth->Instance->MACMIIAR = tmpreg1; in HAL_ETH_ReadPHYRegister()
2106 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) in HAL_ETH_ReadPHYRegister()
2114 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_ReadPHYRegister()
2135 uint32_t tmpreg1; in HAL_ETH_WritePHYRegister() local
2139 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_WritePHYRegister()
2142 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; in HAL_ETH_WritePHYRegister()
2145 …tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device addres… in HAL_ETH_WritePHYRegister()
2146 …tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register addr… in HAL_ETH_WritePHYRegister()
2147 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ in HAL_ETH_WritePHYRegister()
2148 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ in HAL_ETH_WritePHYRegister()
2154 heth->Instance->MACMIIAR = tmpreg1; in HAL_ETH_WritePHYRegister()
2160 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) in HAL_ETH_WritePHYRegister()
2168 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_WritePHYRegister()
2389 uint32_t tmpreg1; in HAL_ETH_SetMACFilterConfig() local
2412 tmpreg1 = (heth->Instance)->MACFFR; in HAL_ETH_SetMACFilterConfig()
2414 (heth->Instance)->MACFFR = tmpreg1; in HAL_ETH_SetMACFilterConfig()
2502 uint32_t tmpreg1; in HAL_ETH_SetHashTable() local
2512 tmpreg1 = (heth->Instance)->MACHTHR; in HAL_ETH_SetHashTable()
2514 (heth->Instance)->MACHTHR = tmpreg1; in HAL_ETH_SetHashTable()
2520 tmpreg1 = (heth->Instance)->MACHTLR; in HAL_ETH_SetHashTable()
2522 (heth->Instance)->MACHTLR = tmpreg1; in HAL_ETH_SetHashTable()
2538 uint32_t tmpreg1; in HAL_ETH_SetRxVLANIdentifier() local
2551 tmpreg1 = (heth->Instance)->MACVLANTR; in HAL_ETH_SetRxVLANIdentifier()
2553 (heth->Instance)->MACVLANTR = tmpreg1; in HAL_ETH_SetRxVLANIdentifier()
2584 uint32_t tmpreg1; in HAL_ETH_ExitPowerDownMode() local
2591 tmpreg1 = (heth->Instance)->MACPMTCSR; in HAL_ETH_ExitPowerDownMode()
2593 (heth->Instance)->MACPMTCSR = tmpreg1; in HAL_ETH_ExitPowerDownMode()
2602 tmpreg1 = (heth->Instance)->MACPMTCSR; in HAL_ETH_ExitPowerDownMode()
2604 (heth->Instance)->MACPMTCSR = tmpreg1; in HAL_ETH_ExitPowerDownMode()
2751 uint32_t tmpreg1; in ETH_SetMACConfig() local
2755 tmpreg1 = (heth->Instance)->MACCR; in ETH_SetMACConfig()
2757 tmpreg1 &= ETH_MACCR_CLEAR_MASK; in ETH_SetMACConfig()
2759 tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | in ETH_SetMACConfig()
2775 (heth->Instance)->MACCR = (uint32_t)tmpreg1; in ETH_SetMACConfig()
2779 tmpreg1 = (heth->Instance)->MACCR; in ETH_SetMACConfig()
2781 (heth->Instance)->MACCR = tmpreg1; in ETH_SetMACConfig()
2786 tmpreg1 = (heth->Instance)->MACFCR; in ETH_SetMACConfig()
2788 tmpreg1 &= ETH_MACFCR_CLEAR_MASK; in ETH_SetMACConfig()
2790 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | in ETH_SetMACConfig()
2798 (heth->Instance)->MACFCR = (uint32_t)tmpreg1; in ETH_SetMACConfig()
2802 tmpreg1 = (heth->Instance)->MACFCR; in ETH_SetMACConfig()
2804 (heth->Instance)->MACFCR = tmpreg1; in ETH_SetMACConfig()
2809 uint32_t tmpreg1; in ETH_SetDMAConfig() local
2813 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_SetDMAConfig()
2815 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; in ETH_SetDMAConfig()
2817 …tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << … in ETH_SetDMAConfig()
2828 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; in ETH_SetDMAConfig()
2832 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_SetDMAConfig()
2834 (heth->Instance)->DMAOMR = tmpreg1; in ETH_SetDMAConfig()
2849 tmpreg1 = (heth->Instance)->DMABMR; in ETH_SetDMAConfig()
2851 (heth->Instance)->DMABMR = tmpreg1; in ETH_SetDMAConfig()
2927 uint32_t tmpreg1; in ETH_MACAddressConfig() local
2933 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; in ETH_MACAddressConfig()
2935 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; in ETH_MACAddressConfig()
2937 …tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) |… in ETH_MACAddressConfig()
2940 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; in ETH_MACAddressConfig()