342         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_DeInit()
359   hdma2d->Instance->FGPFCCR  =    0U;  in HAL_DMA2D_DeInit()
957     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_EnableCLUT()
1007     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad()
1011     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad()
1065     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad_IT()
1072     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad_IT()
1125     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad()
1129     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad()
1185     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad_IT()
1192     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad_IT()
1218     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Abort()
1276     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Suspend()
1349       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_CLUTLoading_Resume()
1428   layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;  in HAL_DMA2D_PollForTransfer()
1791     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);  in HAL_DMA2D_ConfigLayer()
1856     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_ConfigCLUT()