Lines Matching refs:hdma
132 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…
133 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
134 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
170 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) in HAL_DMA_Init() argument
177 if(hdma == NULL) in HAL_DMA_Init()
183 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_Init()
184 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); in HAL_DMA_Init()
185 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); in HAL_DMA_Init()
186 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); in HAL_DMA_Init()
187 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); in HAL_DMA_Init()
188 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); in HAL_DMA_Init()
189 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); in HAL_DMA_Init()
190 assert_param(IS_DMA_MODE(hdma->Init.Mode)); in HAL_DMA_Init()
191 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); in HAL_DMA_Init()
192 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); in HAL_DMA_Init()
195 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) in HAL_DMA_Init()
197 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); in HAL_DMA_Init()
198 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); in HAL_DMA_Init()
199 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); in HAL_DMA_Init()
203 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Init()
206 __HAL_UNLOCK(hdma); in HAL_DMA_Init()
209 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Init()
212 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Init()
218 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Init()
221 hdma->State = HAL_DMA_STATE_TIMEOUT; in HAL_DMA_Init()
228 tmp = hdma->Instance->CR; in HAL_DMA_Init()
237 tmp |= hdma->Init.Channel | hdma->Init.Direction | in HAL_DMA_Init()
238 hdma->Init.PeriphInc | hdma->Init.MemInc | in HAL_DMA_Init()
239 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | in HAL_DMA_Init()
240 hdma->Init.Mode | hdma->Init.Priority; in HAL_DMA_Init()
243 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
246 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; in HAL_DMA_Init()
250 hdma->Instance->CR = tmp; in HAL_DMA_Init()
253 tmp = hdma->Instance->FCR; in HAL_DMA_Init()
259 tmp |= hdma->Init.FIFOMode; in HAL_DMA_Init()
262 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
265 tmp |= hdma->Init.FIFOThreshold; in HAL_DMA_Init()
269 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) in HAL_DMA_Init()
271 if (DMA_CheckFifoParam(hdma) != HAL_OK) in HAL_DMA_Init()
274 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; in HAL_DMA_Init()
277 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
285 hdma->Instance->FCR = tmp; in HAL_DMA_Init()
289 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_Init()
292 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Init()
295 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Init()
298 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
309 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) in HAL_DMA_DeInit() argument
314 if(hdma == NULL) in HAL_DMA_DeInit()
320 if(hdma->State == HAL_DMA_STATE_BUSY) in HAL_DMA_DeInit()
327 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_DeInit()
330 __HAL_DMA_DISABLE(hdma); in HAL_DMA_DeInit()
333 hdma->Instance->CR = 0U; in HAL_DMA_DeInit()
336 hdma->Instance->NDTR = 0U; in HAL_DMA_DeInit()
339 hdma->Instance->PAR = 0U; in HAL_DMA_DeInit()
342 hdma->Instance->M0AR = 0U; in HAL_DMA_DeInit()
345 hdma->Instance->M1AR = 0U; in HAL_DMA_DeInit()
348 hdma->Instance->FCR = 0x00000021U; in HAL_DMA_DeInit()
351 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_DeInit()
354 hdma->XferCpltCallback = NULL; in HAL_DMA_DeInit()
355 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_DeInit()
356 hdma->XferM1CpltCallback = NULL; in HAL_DMA_DeInit()
357 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_DeInit()
358 hdma->XferErrorCallback = NULL; in HAL_DMA_DeInit()
359 hdma->XferAbortCallback = NULL; in HAL_DMA_DeInit()
362 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_DeInit()
365 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_DeInit()
368 hdma->State = HAL_DMA_STATE_RESET; in HAL_DMA_DeInit()
371 __HAL_UNLOCK(hdma); in HAL_DMA_DeInit()
407 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, … in HAL_DMA_Start() argument
415 __HAL_LOCK(hdma); in HAL_DMA_Start()
417 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start()
420 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start()
423 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start()
426 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start()
429 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start()
434 __HAL_UNLOCK(hdma); in HAL_DMA_Start()
451 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres… in HAL_DMA_Start_IT() argument
456 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Start_IT()
462 __HAL_LOCK(hdma); in HAL_DMA_Start_IT()
464 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start_IT()
467 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start_IT()
470 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start_IT()
473 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start_IT()
476 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Start_IT()
479 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; in HAL_DMA_Start_IT()
481 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_Start_IT()
483 hdma->Instance->CR |= DMA_IT_HT; in HAL_DMA_Start_IT()
487 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start_IT()
492 __HAL_UNLOCK(hdma); in HAL_DMA_Start_IT()
513 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort() argument
516 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Abort()
520 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort()
522 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort()
525 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
532 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_Abort()
533 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
535 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_Abort()
537 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_Abort()
541 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort()
544 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Abort()
550 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Abort()
553 hdma->State = HAL_DMA_STATE_TIMEOUT; in HAL_DMA_Abort()
556 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
563 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Abort()
566 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort()
569 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
580 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort_IT() argument
582 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort_IT()
584 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort_IT()
590 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_Abort_IT()
593 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort_IT()
610 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com… in HAL_DMA_PollForTransfer() argument
620 if(HAL_DMA_STATE_BUSY != hdma->State) in HAL_DMA_PollForTransfer()
623 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_PollForTransfer()
624 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
629 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) in HAL_DMA_PollForTransfer()
631 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; in HAL_DMA_PollForTransfer()
639 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
644 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
647 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_PollForTransfer()
650 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) in HAL_DMA_PollForTransfer()
658 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_PollForTransfer()
661 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
664 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
673 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
676 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_PollForTransfer()
679 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
682 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
685 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_PollForTransfer()
688 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
691 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
694 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_PollForTransfer()
697 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
701 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_PollForTransfer()
703 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) in HAL_DMA_PollForTransfer()
705 HAL_DMA_Abort(hdma); in HAL_DMA_PollForTransfer()
708 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
711 hdma->State= HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
714 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
724 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
726 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
729 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
734 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
746 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) in HAL_DMA_IRQHandler() argument
753 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_IRQHandler()
758 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
760 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) in HAL_DMA_IRQHandler()
763 hdma->Instance->CR &= ~(DMA_IT_TE); in HAL_DMA_IRQHandler()
766 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
769 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_IRQHandler()
773 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
775 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) in HAL_DMA_IRQHandler()
778 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
781 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_IRQHandler()
785 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
787 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) in HAL_DMA_IRQHandler()
790 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
793 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_IRQHandler()
797 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
799 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) in HAL_DMA_IRQHandler()
802 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
805 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) in HAL_DMA_IRQHandler()
808 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) in HAL_DMA_IRQHandler()
810 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
813 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
819 if(hdma->XferM1HalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
822 hdma->XferM1HalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
829 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) in HAL_DMA_IRQHandler()
832 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
835 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
838 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
844 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
846 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) in HAL_DMA_IRQHandler()
849 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
851 if(HAL_DMA_STATE_ABORT == hdma->State) in HAL_DMA_IRQHandler()
854 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_IRQHandler()
855 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
857 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_IRQHandler()
859 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
863 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_IRQHandler()
866 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
869 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
871 if(hdma->XferAbortCallback != NULL) in HAL_DMA_IRQHandler()
873 hdma->XferAbortCallback(hdma); in HAL_DMA_IRQHandler()
878 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) in HAL_DMA_IRQHandler()
881 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) in HAL_DMA_IRQHandler()
883 if(hdma->XferM1CpltCallback != NULL) in HAL_DMA_IRQHandler()
886 hdma->XferM1CpltCallback(hdma); in HAL_DMA_IRQHandler()
892 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
895 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
902 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) in HAL_DMA_IRQHandler()
905 hdma->Instance->CR &= ~(DMA_IT_TC); in HAL_DMA_IRQHandler()
908 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
911 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
914 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
917 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
924 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_IRQHandler()
926 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) in HAL_DMA_IRQHandler()
928 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_IRQHandler()
931 __HAL_DMA_DISABLE(hdma); in HAL_DMA_IRQHandler()
940 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); in HAL_DMA_IRQHandler()
943 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
946 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
949 if(hdma->XferErrorCallback != NULL) in HAL_DMA_IRQHandler()
952 hdma->XferErrorCallback(hdma); in HAL_DMA_IRQHandler()
967 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb… in HAL_DMA_RegisterCallback() argument
973 __HAL_LOCK(hdma); in HAL_DMA_RegisterCallback()
975 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_RegisterCallback()
980 hdma->XferCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
984 hdma->XferHalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
988 hdma->XferM1CpltCallback = pCallback; in HAL_DMA_RegisterCallback()
992 hdma->XferM1HalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
996 hdma->XferErrorCallback = pCallback; in HAL_DMA_RegisterCallback()
1000 hdma->XferAbortCallback = pCallback; in HAL_DMA_RegisterCallback()
1016 __HAL_UNLOCK(hdma); in HAL_DMA_RegisterCallback()
1029 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal… in HAL_DMA_UnRegisterCallback() argument
1034 __HAL_LOCK(hdma); in HAL_DMA_UnRegisterCallback()
1036 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_UnRegisterCallback()
1041 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1045 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1049 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1053 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1057 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1061 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1065 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1066 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1067 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1068 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1069 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1070 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1084 __HAL_UNLOCK(hdma); in HAL_DMA_UnRegisterCallback()
1114 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) in HAL_DMA_GetState() argument
1116 return hdma->State; in HAL_DMA_GetState()
1125 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) in HAL_DMA_GetError() argument
1127 return hdma->ErrorCode; in HAL_DMA_GetError()
1151 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32… in DMA_SetConfig() argument
1154 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); in DMA_SetConfig()
1157 hdma->Instance->NDTR = DataLength; in DMA_SetConfig()
1160 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) in DMA_SetConfig()
1163 hdma->Instance->PAR = DstAddress; in DMA_SetConfig()
1166 hdma->Instance->M0AR = SrcAddress; in DMA_SetConfig()
1172 hdma->Instance->PAR = SrcAddress; in DMA_SetConfig()
1175 hdma->Instance->M0AR = DstAddress; in DMA_SetConfig()
1185 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) in DMA_CalcBaseAndBitshift() argument
1187 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; in DMA_CalcBaseAndBitshift()
1191 hdma->StreamIndex = flagBitshiftOffset[stream_number]; in DMA_CalcBaseAndBitshift()
1196 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); in DMA_CalcBaseAndBitshift()
1201 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); in DMA_CalcBaseAndBitshift()
1204 return hdma->StreamBaseAddress; in DMA_CalcBaseAndBitshift()
1213 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) in DMA_CheckFifoParam() argument
1216 uint32_t tmp = hdma->Init.FIFOThreshold; in DMA_CheckFifoParam()
1219 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) in DMA_CheckFifoParam()
1225 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1231 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1244 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) in DMA_CheckFifoParam()
1253 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1259 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1280 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()