Lines Matching refs:OutputClock

383   assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));  in HAL_DFSDM_ChannelInit()
437     assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));  in HAL_DFSDM_ChannelInit()
440     channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;  in HAL_DFSDM_ChannelInit()
444     if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)  in HAL_DFSDM_ChannelInit()
446       assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));  in HAL_DFSDM_ChannelInit()
448       channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<  in HAL_DFSDM_ChannelInit()
516     assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));  in HAL_DFSDM_ChannelInit()
519     DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;  in HAL_DFSDM_ChannelInit()
523     if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)  in HAL_DFSDM_ChannelInit()
525       assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));  in HAL_DFSDM_ChannelInit()
527       DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<  in HAL_DFSDM_ChannelInit()