Lines Matching refs:TIMx
1116 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) in LL_TIM_EnableCounter() argument
1118 SET_BIT(TIMx->CR1, TIM_CR1_CEN); in LL_TIM_EnableCounter()
1127 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) in LL_TIM_DisableCounter() argument
1129 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); in LL_TIM_DisableCounter()
1138 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledCounter() argument
1140 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); in LL_TIM_IsEnabledCounter()
1149 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) in LL_TIM_EnableUpdateEvent() argument
1151 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); in LL_TIM_EnableUpdateEvent()
1160 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) in LL_TIM_DisableUpdateEvent() argument
1162 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); in LL_TIM_DisableUpdateEvent()
1171 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledUpdateEvent() argument
1173 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); in LL_TIM_IsEnabledUpdateEvent()
1192 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) in LL_TIM_SetUpdateSource() argument
1194 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); in LL_TIM_SetUpdateSource()
1205 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) in LL_TIM_GetUpdateSource() argument
1207 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); in LL_TIM_GetUpdateSource()
1219 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) in LL_TIM_SetOnePulseMode() argument
1221 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); in LL_TIM_SetOnePulseMode()
1232 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) in LL_TIM_GetOnePulseMode() argument
1234 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); in LL_TIM_GetOnePulseMode()
1256 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) in LL_TIM_SetCounterMode() argument
1258 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); in LL_TIM_SetCounterMode()
1276 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) in LL_TIM_GetCounterMode() argument
1280 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); in LL_TIM_GetCounterMode()
1284 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); in LL_TIM_GetCounterMode()
1296 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) in LL_TIM_EnableARRPreload() argument
1298 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); in LL_TIM_EnableARRPreload()
1307 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) in LL_TIM_DisableARRPreload() argument
1309 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); in LL_TIM_DisableARRPreload()
1318 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledARRPreload() argument
1320 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); in LL_TIM_IsEnabledARRPreload()
1337 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) in LL_TIM_SetClockDivision() argument
1339 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); in LL_TIM_SetClockDivision()
1355 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) in LL_TIM_GetClockDivision() argument
1357 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); in LL_TIM_GetClockDivision()
1369 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) in LL_TIM_SetCounter() argument
1371 WRITE_REG(TIMx->CNT, Counter); in LL_TIM_SetCounter()
1382 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) in LL_TIM_GetCounter() argument
1384 return (uint32_t)(READ_REG(TIMx->CNT)); in LL_TIM_GetCounter()
1395 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) in LL_TIM_GetDirection() argument
1397 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); in LL_TIM_GetDirection()
1411 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) in LL_TIM_SetPrescaler() argument
1413 WRITE_REG(TIMx->PSC, Prescaler); in LL_TIM_SetPrescaler()
1422 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) in LL_TIM_GetPrescaler() argument
1424 return (uint32_t)(READ_REG(TIMx->PSC)); in LL_TIM_GetPrescaler()
1438 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) in LL_TIM_SetAutoReload() argument
1440 WRITE_REG(TIMx->ARR, AutoReload); in LL_TIM_SetAutoReload()
1451 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) in LL_TIM_GetAutoReload() argument
1453 return (uint32_t)(READ_REG(TIMx->ARR)); in LL_TIM_GetAutoReload()
1465 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) in LL_TIM_SetRepetitionCounter() argument
1467 WRITE_REG(TIMx->RCR, RepetitionCounter); in LL_TIM_SetRepetitionCounter()
1478 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) in LL_TIM_GetRepetitionCounter() argument
1480 return (uint32_t)(READ_REG(TIMx->RCR)); in LL_TIM_GetRepetitionCounter()
1501 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) in LL_TIM_CC_EnablePreload() argument
1503 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); in LL_TIM_CC_EnablePreload()
1514 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) in LL_TIM_CC_DisablePreload() argument
1516 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); in LL_TIM_CC_DisablePreload()
1525 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) in LL_TIM_CC_IsEnabledPreload() argument
1527 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); in LL_TIM_CC_IsEnabledPreload()
1541 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) in LL_TIM_CC_SetUpdate() argument
1543 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); in LL_TIM_CC_SetUpdate()
1555 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) in LL_TIM_CC_SetDMAReqTrigger() argument
1557 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); in LL_TIM_CC_SetDMAReqTrigger()
1568 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) in LL_TIM_CC_GetDMAReqTrigger() argument
1570 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); in LL_TIM_CC_GetDMAReqTrigger()
1587 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) in LL_TIM_CC_SetLockLevel() argument
1589 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); in LL_TIM_CC_SetLockLevel()
1612 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) in LL_TIM_CC_EnableChannel() argument
1614 SET_BIT(TIMx->CCER, Channels); in LL_TIM_CC_EnableChannel()
1637 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) in LL_TIM_CC_DisableChannel() argument
1639 CLEAR_BIT(TIMx->CCER, Channels); in LL_TIM_CC_DisableChannel()
1662 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) in LL_TIM_CC_IsEnabledChannel() argument
1664 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); in LL_TIM_CC_IsEnabledChannel()
1699 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura… in LL_TIM_OC_ConfigOutput() argument
1702 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_ConfigOutput()
1704 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_OC_ConfigOutput()
1706 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), in LL_TIM_OC_ConfigOutput()
1734 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) in LL_TIM_OC_SetMode() argument
1737 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_SetMode()
1763 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_GetMode() argument
1766 …const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCM… in LL_TIM_OC_GetMode()
1793 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) in LL_TIM_OC_SetPolarity() argument
1796 …MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iC… in LL_TIM_OC_SetPolarity()
1821 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_GetPolarity() argument
1824 …return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChann… in LL_TIM_OC_GetPolarity()
1854 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) in LL_TIM_OC_SetIdleState() argument
1857 …MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iCh… in LL_TIM_OC_SetIdleState()
1882 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_GetIdleState() argument
1885 …return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel… in LL_TIM_OC_GetIdleState()
1903 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_EnableFast() argument
1906 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_EnableFast()
1925 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_DisableFast() argument
1928 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_DisableFast()
1947 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_IsEnabledFast() argument
1950 …const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCM… in LL_TIM_OC_IsEnabledFast()
1969 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_EnablePreload() argument
1972 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_EnablePreload()
1990 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_DisablePreload() argument
1993 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_DisablePreload()
2011 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_IsEnabledPreload() argument
2014 …const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCM… in LL_TIM_OC_IsEnabledPreload()
2036 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_EnableClear() argument
2039 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_EnableClear()
2059 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_DisableClear() argument
2062 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_OC_DisableClear()
2084 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_OC_IsEnabledClear() argument
2087 …const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCM… in LL_TIM_OC_IsEnabledClear()
2103 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) in LL_TIM_OC_SetDeadTime() argument
2105 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); in LL_TIM_OC_SetDeadTime()
2120 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH1() argument
2122 WRITE_REG(TIMx->CCR1, CompareValue); in LL_TIM_OC_SetCompareCH1()
2137 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH2() argument
2139 WRITE_REG(TIMx->CCR2, CompareValue); in LL_TIM_OC_SetCompareCH2()
2154 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH3() argument
2156 WRITE_REG(TIMx->CCR3, CompareValue); in LL_TIM_OC_SetCompareCH3()
2171 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) in LL_TIM_OC_SetCompareCH4() argument
2173 WRITE_REG(TIMx->CCR4, CompareValue); in LL_TIM_OC_SetCompareCH4()
2187 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH1() argument
2189 return (uint32_t)(READ_REG(TIMx->CCR1)); in LL_TIM_OC_GetCompareCH1()
2203 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH2() argument
2205 return (uint32_t)(READ_REG(TIMx->CCR2)); in LL_TIM_OC_GetCompareCH2()
2219 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH3() argument
2221 return (uint32_t)(READ_REG(TIMx->CCR3)); in LL_TIM_OC_GetCompareCH3()
2235 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) in LL_TIM_OC_GetCompareCH4() argument
2237 return (uint32_t)(READ_REG(TIMx->CCR4)); in LL_TIM_OC_GetCompareCH4()
2282 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) in LL_TIM_IC_Config() argument
2285 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_IC_Config()
2289 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
2311 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv… in LL_TIM_IC_SetActiveInput() argument
2314 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_IC_SetActiveInput()
2335 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetActiveInput() argument
2338 …const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCM… in LL_TIM_IC_GetActiveInput()
2361 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal… in LL_TIM_IC_SetPrescaler() argument
2364 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_IC_SetPrescaler()
2386 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetPrescaler() argument
2389 …const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCM… in LL_TIM_IC_GetPrescaler()
2424 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) in LL_TIM_IC_SetFilter() argument
2427 …__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iCh… in LL_TIM_IC_SetFilter()
2461 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetFilter() argument
2464 …const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCM… in LL_TIM_IC_GetFilter()
2490 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) in LL_TIM_IC_SetPolarity() argument
2493 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
2518 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) in LL_TIM_IC_GetPolarity() argument
2521 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
2533 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) in LL_TIM_IC_EnableXORCombination() argument
2535 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); in LL_TIM_IC_EnableXORCombination()
2546 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) in LL_TIM_IC_DisableXORCombination() argument
2548 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); in LL_TIM_IC_DisableXORCombination()
2559 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) in LL_TIM_IC_IsEnabledXORCombination() argument
2561 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); in LL_TIM_IC_IsEnabledXORCombination()
2575 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH1() argument
2577 return (uint32_t)(READ_REG(TIMx->CCR1)); in LL_TIM_IC_GetCaptureCH1()
2591 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH2() argument
2593 return (uint32_t)(READ_REG(TIMx->CCR2)); in LL_TIM_IC_GetCaptureCH2()
2607 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH3() argument
2609 return (uint32_t)(READ_REG(TIMx->CCR3)); in LL_TIM_IC_GetCaptureCH3()
2623 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) in LL_TIM_IC_GetCaptureCH4() argument
2625 return (uint32_t)(READ_REG(TIMx->CCR4)); in LL_TIM_IC_GetCaptureCH4()
2644 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) in LL_TIM_EnableExternalClock() argument
2646 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); in LL_TIM_EnableExternalClock()
2657 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) in LL_TIM_DisableExternalClock() argument
2659 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); in LL_TIM_DisableExternalClock()
2670 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledExternalClock() argument
2672 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); in LL_TIM_IsEnabledExternalClock()
2694 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) in LL_TIM_SetClockSource() argument
2696 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); in LL_TIM_SetClockSource()
2711 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) in LL_TIM_SetEncoderMode() argument
2713 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); in LL_TIM_SetEncoderMode()
2740 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) in LL_TIM_SetTriggerOutput() argument
2742 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); in LL_TIM_SetTriggerOutput()
2758 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) in LL_TIM_SetSlaveMode() argument
2760 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); in LL_TIM_SetSlaveMode()
2780 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) in LL_TIM_SetTriggerInput() argument
2782 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); in LL_TIM_SetTriggerInput()
2793 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) in LL_TIM_EnableMasterSlaveMode() argument
2795 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); in LL_TIM_EnableMasterSlaveMode()
2806 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) in LL_TIM_DisableMasterSlaveMode() argument
2808 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); in LL_TIM_DisableMasterSlaveMode()
2819 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledMasterSlaveMode() argument
2821 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); in LL_TIM_IsEnabledMasterSlaveMode()
2859 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale… in LL_TIM_ConfigETR() argument
2862 …MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | E… in LL_TIM_ConfigETR()
2880 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) in LL_TIM_EnableBRK() argument
2883 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); in LL_TIM_EnableBRK()
2885 tmpreg = READ_REG(TIMx->BDTR); in LL_TIM_EnableBRK()
2897 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) in LL_TIM_DisableBRK() argument
2900 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); in LL_TIM_DisableBRK()
2902 tmpreg = READ_REG(TIMx->BDTR); in LL_TIM_DisableBRK()
2917 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) in LL_TIM_ConfigBRK() argument
2920 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); in LL_TIM_ConfigBRK()
2922 tmpreg = READ_REG(TIMx->BDTR); in LL_TIM_ConfigBRK()
2941 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat… in LL_TIM_SetOffStates() argument
2943 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); in LL_TIM_SetOffStates()
2954 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) in LL_TIM_EnableAutomaticOutput() argument
2956 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); in LL_TIM_EnableAutomaticOutput()
2967 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) in LL_TIM_DisableAutomaticOutput() argument
2969 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); in LL_TIM_DisableAutomaticOutput()
2980 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledAutomaticOutput() argument
2982 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAutomaticOutput()
2995 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) in LL_TIM_EnableAllOutputs() argument
2997 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); in LL_TIM_EnableAllOutputs()
3010 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) in LL_TIM_DisableAllOutputs() argument
3012 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); in LL_TIM_DisableAllOutputs()
3023 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledAllOutputs() argument
3025 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); in LL_TIM_IsEnabledAllOutputs()
3082 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_… in LL_TIM_ConfigDMABurst() argument
3084 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); in LL_TIM_ConfigDMABurst()
3152 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) in LL_TIM_SetRemap() argument
3165 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); in LL_TIM_SetRemap()
3168 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); in LL_TIM_SetRemap()
3185 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_UPDATE() argument
3187 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); in LL_TIM_ClearFlag_UPDATE()
3196 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_UPDATE() argument
3198 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_UPDATE()
3207 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC1() argument
3209 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); in LL_TIM_ClearFlag_CC1()
3218 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC1() argument
3220 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC1()
3229 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC2() argument
3231 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); in LL_TIM_ClearFlag_CC2()
3240 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC2() argument
3242 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC2()
3251 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC3() argument
3253 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); in LL_TIM_ClearFlag_CC3()
3262 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC3() argument
3264 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC3()
3273 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC4() argument
3275 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); in LL_TIM_ClearFlag_CC4()
3284 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC4() argument
3286 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC4()
3295 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_COM() argument
3297 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); in LL_TIM_ClearFlag_COM()
3306 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_COM() argument
3308 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_COM()
3317 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_TRIG() argument
3319 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); in LL_TIM_ClearFlag_TRIG()
3328 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_TRIG() argument
3330 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_TRIG()
3339 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_BRK() argument
3341 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); in LL_TIM_ClearFlag_BRK()
3350 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_BRK() argument
3352 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_BRK()
3361 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC1OVR() argument
3363 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); in LL_TIM_ClearFlag_CC1OVR()
3373 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC1OVR() argument
3375 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC1OVR()
3384 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC2OVR() argument
3386 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); in LL_TIM_ClearFlag_CC2OVR()
3396 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC2OVR() argument
3398 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC2OVR()
3407 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC3OVR() argument
3409 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); in LL_TIM_ClearFlag_CC3OVR()
3419 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC3OVR() argument
3421 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC3OVR()
3430 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) in LL_TIM_ClearFlag_CC4OVR() argument
3432 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); in LL_TIM_ClearFlag_CC4OVR()
3442 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) in LL_TIM_IsActiveFlag_CC4OVR() argument
3444 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); in LL_TIM_IsActiveFlag_CC4OVR()
3460 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_UPDATE() argument
3462 SET_BIT(TIMx->DIER, TIM_DIER_UIE); in LL_TIM_EnableIT_UPDATE()
3471 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_UPDATE() argument
3473 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); in LL_TIM_DisableIT_UPDATE()
3482 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_UPDATE() argument
3484 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_UPDATE()
3493 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC1() argument
3495 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); in LL_TIM_EnableIT_CC1()
3504 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC1() argument
3506 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); in LL_TIM_DisableIT_CC1()
3515 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC1() argument
3517 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC1()
3526 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC2() argument
3528 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); in LL_TIM_EnableIT_CC2()
3537 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC2() argument
3539 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); in LL_TIM_DisableIT_CC2()
3548 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC2() argument
3550 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC2()
3559 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC3() argument
3561 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); in LL_TIM_EnableIT_CC3()
3570 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC3() argument
3572 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); in LL_TIM_DisableIT_CC3()
3581 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC3() argument
3583 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC3()
3592 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_CC4() argument
3594 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); in LL_TIM_EnableIT_CC4()
3603 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_CC4() argument
3605 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); in LL_TIM_DisableIT_CC4()
3614 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_CC4() argument
3616 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_CC4()
3625 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_COM() argument
3627 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); in LL_TIM_EnableIT_COM()
3636 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_COM() argument
3638 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); in LL_TIM_DisableIT_COM()
3647 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_COM() argument
3649 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_COM()
3658 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_TRIG() argument
3660 SET_BIT(TIMx->DIER, TIM_DIER_TIE); in LL_TIM_EnableIT_TRIG()
3669 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_TRIG() argument
3671 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); in LL_TIM_DisableIT_TRIG()
3680 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_TRIG() argument
3682 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_TRIG()
3691 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) in LL_TIM_EnableIT_BRK() argument
3693 SET_BIT(TIMx->DIER, TIM_DIER_BIE); in LL_TIM_EnableIT_BRK()
3702 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) in LL_TIM_DisableIT_BRK() argument
3704 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); in LL_TIM_DisableIT_BRK()
3713 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledIT_BRK() argument
3715 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); in LL_TIM_IsEnabledIT_BRK()
3731 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_UPDATE() argument
3733 SET_BIT(TIMx->DIER, TIM_DIER_UDE); in LL_TIM_EnableDMAReq_UPDATE()
3742 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_UPDATE() argument
3744 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); in LL_TIM_DisableDMAReq_UPDATE()
3753 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_UPDATE() argument
3755 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_UPDATE()
3764 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC1() argument
3766 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); in LL_TIM_EnableDMAReq_CC1()
3775 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC1() argument
3777 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); in LL_TIM_DisableDMAReq_CC1()
3786 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC1() argument
3788 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC1()
3797 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC2() argument
3799 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); in LL_TIM_EnableDMAReq_CC2()
3808 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC2() argument
3810 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); in LL_TIM_DisableDMAReq_CC2()
3819 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC2() argument
3821 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC2()
3830 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC3() argument
3832 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); in LL_TIM_EnableDMAReq_CC3()
3841 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC3() argument
3843 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); in LL_TIM_DisableDMAReq_CC3()
3852 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC3() argument
3854 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC3()
3863 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_CC4() argument
3865 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); in LL_TIM_EnableDMAReq_CC4()
3874 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_CC4() argument
3876 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); in LL_TIM_DisableDMAReq_CC4()
3885 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_CC4() argument
3887 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_CC4()
3896 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_COM() argument
3898 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); in LL_TIM_EnableDMAReq_COM()
3907 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_COM() argument
3909 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); in LL_TIM_DisableDMAReq_COM()
3918 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_COM() argument
3920 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_COM()
3929 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) in LL_TIM_EnableDMAReq_TRIG() argument
3931 SET_BIT(TIMx->DIER, TIM_DIER_TDE); in LL_TIM_EnableDMAReq_TRIG()
3940 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) in LL_TIM_DisableDMAReq_TRIG() argument
3942 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); in LL_TIM_DisableDMAReq_TRIG()
3951 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) in LL_TIM_IsEnabledDMAReq_TRIG() argument
3953 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); in LL_TIM_IsEnabledDMAReq_TRIG()
3969 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_UPDATE() argument
3971 SET_BIT(TIMx->EGR, TIM_EGR_UG); in LL_TIM_GenerateEvent_UPDATE()
3980 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC1() argument
3982 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); in LL_TIM_GenerateEvent_CC1()
3991 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC2() argument
3993 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); in LL_TIM_GenerateEvent_CC2()
4002 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC3() argument
4004 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); in LL_TIM_GenerateEvent_CC3()
4013 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_CC4() argument
4015 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); in LL_TIM_GenerateEvent_CC4()
4024 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_COM() argument
4026 SET_BIT(TIMx->EGR, TIM_EGR_COMG); in LL_TIM_GenerateEvent_COM()
4035 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_TRIG() argument
4037 SET_BIT(TIMx->EGR, TIM_EGR_TG); in LL_TIM_GenerateEvent_TRIG()
4046 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) in LL_TIM_GenerateEvent_BRK() argument
4048 SET_BIT(TIMx->EGR, TIM_EGR_BG); in LL_TIM_GenerateEvent_BRK()
4060 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4062 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4064 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC…
4066 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC…
4068 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderIni…
4070 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_Hall…
4072 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);