Lines Matching refs:APB1ENR

470                                              SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
472                                              tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
477                                              SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
479                                              tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
484                                              SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
486                                              tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
491                                                SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
493 …                                            tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
498                                              SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
500                                              tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
505                                              SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
507                                              tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
512                                             SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
514                                             tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
518 #define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
519 #define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
520 #define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
521 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
522 #define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
523 #define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
524 #define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
536 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
537 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
538 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
539 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
540 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
541 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
542 #define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
544 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
545 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
546 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
547 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
548 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
549 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
550 #define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)