Lines Matching refs:AHB1PERIPH_BASE
788 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) macro
846 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)
847 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)
848 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)
849 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)
850 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)
851 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)
852 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)
853 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)
854 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)
855 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)
856 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)
857 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)
858 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)
859 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)
860 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)
861 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
865 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)
866 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)