Lines Matching refs:AHB1PERIPH_BASE
708 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) macro
763 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)
764 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)
765 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)
766 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)
767 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)
768 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)
769 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)
770 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)
771 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)
772 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)
773 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)
774 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)
775 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)
776 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)
777 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)
778 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
782 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)
783 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)