Lines Matching refs:AHB1PERIPH_BASE
761 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) macro
811 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)
812 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)
813 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)
814 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)
815 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)
816 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)
817 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)
818 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)
819 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)
820 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)
821 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)
822 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)
823 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)
824 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)
825 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)
826 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
830 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)
831 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)