Lines Matching refs:AHB1PERIPH_BASE
699 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) macro
747 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)
748 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)
749 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)
750 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)
751 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)
752 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)
753 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)
754 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)
755 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)
756 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)
757 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)
758 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)
759 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)
760 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)
761 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)
762 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
766 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)
767 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)