691   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
706   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
718   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
721   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
744   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
880   uint32_t tmpcr2;  in OC1Config()  local
895   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
926     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
929     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
933   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
959   uint32_t tmpcr2;  in OC2Config()  local
974   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
1005     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
1010     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
1015   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
1041   uint32_t tmpcr2;  in OC3Config()  local
1056   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
1089     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
1092     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
1097   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1123   uint32_t tmpcr2;  in OC4Config()  local
1138   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1162     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1167   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()