613   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
619   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
646   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
703   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
712   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
753   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
889   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
892   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
942   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
968   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
971   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
1024   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
1050   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
1053   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1106   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1132   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1135   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1176   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1205   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1208   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1239   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1269   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1272   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1302   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1326   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1334   MODIFY_REG(TIMx->CCER,  in IC1Config()
1359   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1367   MODIFY_REG(TIMx->CCER,  in IC2Config()
1392   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1400   MODIFY_REG(TIMx->CCER,  in IC3Config()
1425   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1433   MODIFY_REG(TIMx->CCER,  in IC4Config()