201 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Init()  argument
209   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Init()
226   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
271   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FMC_NORSRAM_Init()
276     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
289 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_DeInit()  argument
293   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_DeInit()
298   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
304     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
309     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
312   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
326 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Timing_Init()  argument
332   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Timing_Init()
343   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
353   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))  in FMC_NORSRAM_Timing_Init()
355     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));  in FMC_NORSRAM_Timing_Init()
357     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);  in FMC_NORSRAM_Timing_Init()
375 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,  in FMC_NORSRAM_Extended_Timing_Init()  argument
386     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  in FMC_NORSRAM_Extended_Timing_Init()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
401     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
431 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
434   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Enable()
438   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
449 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
452   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Disable()
456   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
521 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)  in FMC_NAND_Init()  argument
524   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_Init()
537 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FMC_NAND_Init()
548 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FMC_NAND_Init()
568 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_CommonSpace_Timing_Init()  argument
572   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_CommonSpace_Timing_Init()
583 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FMC_NAND_CommonSpace_Timing_Init()
591 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FMC_NAND_CommonSpace_Timing_Init()
608 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_AttributeSpace_Timing_Init()  argument
612   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_AttributeSpace_Timing_Init()
623 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FMC_NAND_AttributeSpace_Timing_Init()
631 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FMC_NAND_AttributeSpace_Timing_Init()
646 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
649   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_DeInit()
653   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
659     WRITE_REG(Device->PCR2,  0x00000018U);  in FMC_NAND_DeInit()
660     WRITE_REG(Device->SR2,   0x00000040U);  in FMC_NAND_DeInit()
661     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
662     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
668     WRITE_REG(Device->PCR3,  0x00000018U);  in FMC_NAND_DeInit()
669     WRITE_REG(Device->SR3,   0x00000040U);  in FMC_NAND_DeInit()
670     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
671     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
703 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
706   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Enable()
712     SET_BIT(Device->PCR2, FMC_PCRx_ECCEN);  in FMC_NAND_ECC_Enable()
716     SET_BIT(Device->PCR3, FMC_PCRx_ECCEN);  in FMC_NAND_ECC_Enable()
729 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
732   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Disable()
738     CLEAR_BIT(Device->PCR2, FMC_PCRx_ECCEN);  in FMC_NAND_ECC_Disable()
742     CLEAR_BIT(Device->PCR3, FMC_PCRx_ECCEN);  in FMC_NAND_ECC_Disable()
756 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
762   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_GetECC()
769   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
784     *ECCval = (uint32_t)Device->ECCR2;  in FMC_NAND_GetECC()
789     *ECCval = (uint32_t)Device->ECCR3;  in FMC_NAND_GetECC()
849 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)  in FMC_PCCARD_Init()  argument
852   assert_param(IS_FMC_PCCARD_DEVICE(Device));  in FMC_PCCARD_Init()
860   MODIFY_REG(Device->PCR4,  in FMC_PCCARD_Init()
882 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,  in FMC_PCCARD_CommonSpace_Timing_Init()  argument
886   assert_param(IS_FMC_PCCARD_DEVICE(Device));  in FMC_PCCARD_CommonSpace_Timing_Init()
895   MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,  in FMC_PCCARD_CommonSpace_Timing_Init()
911 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,  in FMC_PCCARD_AttributeSpace_Timing_Init()  argument
915   assert_param(IS_FMC_PCCARD_DEVICE(Device));  in FMC_PCCARD_AttributeSpace_Timing_Init()
924   MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,  in FMC_PCCARD_AttributeSpace_Timing_Init()
940 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,  in FMC_PCCARD_IOSpace_Timing_Init()  argument
944   assert_param(IS_FMC_PCCARD_DEVICE(Device));  in FMC_PCCARD_IOSpace_Timing_Init()
953   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,  in FMC_PCCARD_IOSpace_Timing_Init()
967 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)  in FMC_PCCARD_DeInit()  argument
970   assert_param(IS_FMC_PCCARD_DEVICE(Device));  in FMC_PCCARD_DeInit()
973   __FMC_PCCARD_DISABLE(Device);  in FMC_PCCARD_DeInit()
976   Device->PCR4    = 0x00000018U;  in FMC_PCCARD_DeInit()
977   Device->SR4     = 0x00000040U;  in FMC_PCCARD_DeInit()
978   Device->PMEM4   = 0xFCFCFCFCU;  in FMC_PCCARD_DeInit()
979   Device->PATT4   = 0xFCFCFCFCU;  in FMC_PCCARD_DeInit()
980   Device->PIO4    = 0xFCFCFCFCU;  in FMC_PCCARD_DeInit()