Lines Matching refs:Timing
313 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
318 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
319 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Timing_Init()
320 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Timing_Init()
321 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Timing_Init()
322 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); in FSMC_NORSRAM_Timing_Init()
323 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); in FSMC_NORSRAM_Timing_Init()
324 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Timing_Init()
329 (Timing->AddressSetupTime << FSMC_BTR1_ADDSET_Pos) | in FSMC_NORSRAM_Timing_Init()
330 (Timing->AddressHoldTime << FSMC_BTR1_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
331 (Timing->DataSetupTime << FSMC_BTR1_DATAST_Pos) | in FSMC_NORSRAM_Timing_Init()
332 (Timing->BusTurnAroundDuration << FSMC_BTR1_BUSTURN_Pos) | in FSMC_NORSRAM_Timing_Init()
333 ((Timing->CLKDivision - 1U) << FSMC_BTR1_CLKDIV_Pos) | in FSMC_NORSRAM_Timing_Init()
334 ((Timing->DataLatency - 2U) << FSMC_BTR1_DATLAT_Pos) | in FSMC_NORSRAM_Timing_Init()
335 Timing->AccessMode; in FSMC_NORSRAM_Timing_Init()
353 … const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FSMC_NORSRAM_Extended_Timing_Init() argument
364 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
365 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Extended_Timing_Init()
366 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
367 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Extended_Timing_Init()
368 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Extended_Timing_Init()
372 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
373 … ((Timing->AddressHoldTime) << FSMC_BWTR1_ADDHLD_Pos) | in FSMC_NORSRAM_Extended_Timing_Init()
374 … ((Timing->DataSetupTime) << FSMC_BWTR1_DATAST_Pos) | in FSMC_NORSRAM_Extended_Timing_Init()
375 … Timing->AccessMode | in FSMC_NORSRAM_Extended_Timing_Init()
376 … ((Timing->BusTurnAroundDuration) << FSMC_BWTR1_BUSTURN_Pos))); in FSMC_NORSRAM_Extended_Timing_Init()
546 … const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NAND_CommonSpace_Timing_Init() argument
550 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
551 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
552 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
553 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
560 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_CommonSpace_Timing_Init()
561 … ((Timing->WaitSetupTime) << FSMC_PMEM3_MEMWAIT3_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
562 … ((Timing->HoldSetupTime) << FSMC_PMEM3_MEMHOLD3_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
563 … ((Timing->HiZSetupTime) << FSMC_PMEM3_MEMHIZ3_Pos))); in FSMC_NAND_CommonSpace_Timing_Init()
568 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_CommonSpace_Timing_Init()
569 … ((Timing->WaitSetupTime) << FSMC_PMEM3_MEMWAIT3_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
570 … ((Timing->HoldSetupTime) << FSMC_PMEM3_MEMHOLD3_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
571 … ((Timing->HiZSetupTime) << FSMC_PMEM3_MEMHIZ3_Pos))); in FSMC_NAND_CommonSpace_Timing_Init()
586 … const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NAND_AttributeSpace_Timing_Init() argument
590 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
591 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
592 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
593 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
600 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_AttributeSpace_Timing_Init()
601 … ((Timing->WaitSetupTime) << FSMC_PATT3_ATTWAIT3_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
602 … ((Timing->HoldSetupTime) << FSMC_PATT3_ATTHOLD3_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
603 … ((Timing->HiZSetupTime) << FSMC_PATT3_ATTHIZ3_Pos))); in FSMC_NAND_AttributeSpace_Timing_Init()
608 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_AttributeSpace_Timing_Init()
609 … ((Timing->WaitSetupTime) << FSMC_PATT3_ATTWAIT3_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
610 … ((Timing->HoldSetupTime) << FSMC_PATT3_ATTHOLD3_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
611 … ((Timing->HiZSetupTime) << FSMC_PATT3_ATTHIZ3_Pos))); in FSMC_NAND_AttributeSpace_Timing_Init()
858 const FSMC_NAND_PCC_TimingTypeDef *Timing) in FSMC_PCCARD_CommonSpace_Timing_Init() argument
863 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
864 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
865 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
866 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
871 (Timing->SetupTime | in FSMC_PCCARD_CommonSpace_Timing_Init()
872 ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos) | in FSMC_PCCARD_CommonSpace_Timing_Init()
873 ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos) | in FSMC_PCCARD_CommonSpace_Timing_Init()
874 ((Timing->HiZSetupTime) << FSMC_PMEM4_MEMHIZ4_Pos))); in FSMC_PCCARD_CommonSpace_Timing_Init()
887 const FSMC_NAND_PCC_TimingTypeDef *Timing) in FSMC_PCCARD_AttributeSpace_Timing_Init() argument
892 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
893 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
894 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
895 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
900 (Timing->SetupTime | in FSMC_PCCARD_AttributeSpace_Timing_Init()
901 ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos) | in FSMC_PCCARD_AttributeSpace_Timing_Init()
902 ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos) | in FSMC_PCCARD_AttributeSpace_Timing_Init()
903 ((Timing->HiZSetupTime) << FSMC_PATT4_ATTHIZ4_Pos))); in FSMC_PCCARD_AttributeSpace_Timing_Init()
916 const FSMC_NAND_PCC_TimingTypeDef *Timing) in FSMC_PCCARD_IOSpace_Timing_Init() argument
921 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
922 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
923 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
924 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
929 (Timing->SetupTime | in FSMC_PCCARD_IOSpace_Timing_Init()
930 (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | in FSMC_PCCARD_IOSpace_Timing_Init()
931 (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | in FSMC_PCCARD_IOSpace_Timing_Init()
932 (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos))); in FSMC_PCCARD_IOSpace_Timing_Init()