195 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_Init()  argument
203   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_Init()
219   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FSMC_NORSRAM_Init()
262   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FSMC_NORSRAM_Init()
275 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_DeInit()  argument
279   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_DeInit()
284   __FSMC_NORSRAM_DISABLE(Device, Bank);  in FSMC_NORSRAM_DeInit()
290     Device->BTCR[Bank] = 0x000030DBU;  in FSMC_NORSRAM_DeInit()
295     Device->BTCR[Bank] = 0x000030D2U;  in FSMC_NORSRAM_DeInit()
298   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
312 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_Timing_Init()  argument
317   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_Timing_Init()
328   Device->BTCR[Bank + 1U] =  in FSMC_NORSRAM_Timing_Init()
352 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,  in FSMC_NORSRAM_Extended_Timing_Init()  argument
363     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));  in FSMC_NORSRAM_Extended_Timing_Init()
372 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
380     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FSMC_NORSRAM_Extended_Timing_Init()
410 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Enable()  argument
413   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_WriteOperation_Enable()
417   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Enable()
428 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Disable()  argument
431   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_WriteOperation_Disable()
435   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Disable()
498 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init)  in FSMC_NAND_Init()  argument
501   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_Init()
514 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FSMC_NAND_Init()
525 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FSMC_NAND_Init()
545 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,  in FSMC_NAND_CommonSpace_Timing_Init()  argument
549   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_CommonSpace_Timing_Init()
560 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_CommonSpace_Timing_Init()
568 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_CommonSpace_Timing_Init()
585 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,  in FSMC_NAND_AttributeSpace_Timing_Init()  argument
589   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_AttributeSpace_Timing_Init()
600 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_AttributeSpace_Timing_Init()
608 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_AttributeSpace_Timing_Init()
623 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_DeInit()  argument
626   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_DeInit()
630   __FSMC_NAND_DISABLE(Device, Bank);  in FSMC_NAND_DeInit()
636     WRITE_REG(Device->PCR2,  0x00000018U);  in FSMC_NAND_DeInit()
637     WRITE_REG(Device->SR2,   0x00000040U);  in FSMC_NAND_DeInit()
638     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
639     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
645     WRITE_REG(Device->PCR3,  0x00000018U);  in FSMC_NAND_DeInit()
646     WRITE_REG(Device->SR3,   0x00000040U);  in FSMC_NAND_DeInit()
647     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
648     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
680 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Enable()  argument
683   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_ECC_Enable()
689     SET_BIT(Device->PCR2, FSMC_PCR3_ECCEN);  in FSMC_NAND_ECC_Enable()
693     SET_BIT(Device->PCR3, FSMC_PCR3_ECCEN);  in FSMC_NAND_ECC_Enable()
706 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Disable()  argument
709   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_ECC_Disable()
715     CLEAR_BIT(Device->PCR2, FSMC_PCR3_ECCEN);  in FSMC_NAND_ECC_Disable()
719     CLEAR_BIT(Device->PCR3, FSMC_PCR3_ECCEN);  in FSMC_NAND_ECC_Disable()
733 HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FSMC_NAND_GetECC()  argument
739   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_GetECC()
746   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)  in FSMC_NAND_GetECC()
761     *ECCval = (uint32_t)Device->ECCR2;  in FSMC_NAND_GetECC()
766     *ECCval = (uint32_t)Device->ECCR3;  in FSMC_NAND_GetECC()
824 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init)  in FSMC_PCCARD_Init()  argument
827   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_Init()
835   MODIFY_REG(Device->PCR4,  in FSMC_PCCARD_Init()
857 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_CommonSpace_Timing_Init()  argument
861   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_CommonSpace_Timing_Init()
870   MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,  in FSMC_PCCARD_CommonSpace_Timing_Init()
886 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_AttributeSpace_Timing_Init()  argument
890   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_AttributeSpace_Timing_Init()
899   MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,  in FSMC_PCCARD_AttributeSpace_Timing_Init()
915 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_IOSpace_Timing_Init()  argument
919   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_IOSpace_Timing_Init()
928   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,  in FSMC_PCCARD_IOSpace_Timing_Init()
942 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)  in FSMC_PCCARD_DeInit()  argument
945   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_DeInit()
948   __FSMC_PCCARD_DISABLE(Device);  in FSMC_PCCARD_DeInit()
951   Device->PCR4    = 0x00000018U;  in FSMC_PCCARD_DeInit()
952   Device->SR4     = 0x00000040U;  in FSMC_PCCARD_DeInit()
953   Device->PMEM4   = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()
954   Device->PATT4   = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()
955   Device->PIO4    = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()