Lines Matching refs:tmpreg1
212 uint32_t tmpreg1 = 0U, phyreg = 0U; in HAL_ETH_Init() local
283 tmpreg1 = (heth->Instance)->MACMIIAR; in HAL_ETH_Init()
285 tmpreg1 &= ETH_MACMIIAR_CR_MASK; in HAL_ETH_Init()
294 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; in HAL_ETH_Init()
299 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; in HAL_ETH_Init()
304 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; in HAL_ETH_Init()
309 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; in HAL_ETH_Init()
313 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; in HAL_ETH_Init()
1291 uint32_t tmpreg1 = 0U; in HAL_ETH_ReadPHYRegister() local
1306 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_ReadPHYRegister()
1309 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; in HAL_ETH_ReadPHYRegister()
1312 …tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device add… in HAL_ETH_ReadPHYRegister()
1313 …tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register ad… in HAL_ETH_ReadPHYRegister()
1314 …tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode … in HAL_ETH_ReadPHYRegister()
1315 …tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit … in HAL_ETH_ReadPHYRegister()
1318 heth->Instance->MACMIIAR = tmpreg1; in HAL_ETH_ReadPHYRegister()
1324 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) in HAL_ETH_ReadPHYRegister()
1337 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_ReadPHYRegister()
1363 uint32_t tmpreg1 = 0U; in HAL_ETH_WritePHYRegister() local
1378 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_WritePHYRegister()
1381 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; in HAL_ETH_WritePHYRegister()
1384 …tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device add… in HAL_ETH_WritePHYRegister()
1385 …tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register addr… in HAL_ETH_WritePHYRegister()
1386 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ in HAL_ETH_WritePHYRegister()
1387 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ in HAL_ETH_WritePHYRegister()
1393 heth->Instance->MACMIIAR = tmpreg1; in HAL_ETH_WritePHYRegister()
1399 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) in HAL_ETH_WritePHYRegister()
1412 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_WritePHYRegister()
1534 uint32_t tmpreg1 = 0U; in HAL_ETH_ConfigMAC() local
1578 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1580 tmpreg1 &= ETH_MACCR_CLEAR_MASK; in HAL_ETH_ConfigMAC()
1582 tmpreg1 |= (uint32_t)(macconf->Watchdog | in HAL_ETH_ConfigMAC()
1597 (heth->Instance)->MACCR = (uint32_t)tmpreg1; in HAL_ETH_ConfigMAC()
1601 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1603 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_ConfigMAC()
1618 tmpreg1 = (heth->Instance)->MACFFR; in HAL_ETH_ConfigMAC()
1620 (heth->Instance)->MACFFR = tmpreg1; in HAL_ETH_ConfigMAC()
1631 tmpreg1 = (heth->Instance)->MACFCR; in HAL_ETH_ConfigMAC()
1633 tmpreg1 &= ETH_MACFCR_CLEAR_MASK; in HAL_ETH_ConfigMAC()
1635 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | in HAL_ETH_ConfigMAC()
1643 (heth->Instance)->MACFCR = (uint32_t)tmpreg1; in HAL_ETH_ConfigMAC()
1647 tmpreg1 = (heth->Instance)->MACFCR; in HAL_ETH_ConfigMAC()
1649 (heth->Instance)->MACFCR = tmpreg1; in HAL_ETH_ConfigMAC()
1657 tmpreg1 = (heth->Instance)->MACVLANTR; in HAL_ETH_ConfigMAC()
1659 (heth->Instance)->MACVLANTR = tmpreg1; in HAL_ETH_ConfigMAC()
1665 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1668 tmpreg1 &= ~(0x00004800U); in HAL_ETH_ConfigMAC()
1670 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); in HAL_ETH_ConfigMAC()
1673 (heth->Instance)->MACCR = (uint32_t)tmpreg1; in HAL_ETH_ConfigMAC()
1677 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1679 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_ConfigMAC()
1701 uint32_t tmpreg1 = 0U; in HAL_ETH_ConfigDMA() local
1729 tmpreg1 = (heth->Instance)->DMAOMR; in HAL_ETH_ConfigDMA()
1731 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; in HAL_ETH_ConfigDMA()
1733 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | in HAL_ETH_ConfigDMA()
1744 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; in HAL_ETH_ConfigDMA()
1748 tmpreg1 = (heth->Instance)->DMAOMR; in HAL_ETH_ConfigDMA()
1750 (heth->Instance)->DMAOMR = tmpreg1; in HAL_ETH_ConfigDMA()
1764 tmpreg1 = (heth->Instance)->DMABMR; in HAL_ETH_ConfigDMA()
1766 (heth->Instance)->DMABMR = tmpreg1; in HAL_ETH_ConfigDMA()
1835 uint32_t tmpreg1 = 0U; in ETH_MACDMAConfig() local
1886 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACDMAConfig()
1888 tmpreg1 &= ETH_MACCR_CLEAR_MASK; in ETH_MACDMAConfig()
1902 tmpreg1 |= (uint32_t)(macinit.Watchdog | in ETH_MACDMAConfig()
1917 (heth->Instance)->MACCR = (uint32_t)tmpreg1; in ETH_MACDMAConfig()
1921 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACDMAConfig()
1923 (heth->Instance)->MACCR = tmpreg1; in ETH_MACDMAConfig()
1946 tmpreg1 = (heth->Instance)->MACFFR; in ETH_MACDMAConfig()
1948 (heth->Instance)->MACFFR = tmpreg1; in ETH_MACDMAConfig()
1959 tmpreg1 = (heth->Instance)->MACFCR; in ETH_MACDMAConfig()
1961 tmpreg1 &= ETH_MACFCR_CLEAR_MASK; in ETH_MACDMAConfig()
1969 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | in ETH_MACDMAConfig()
1977 (heth->Instance)->MACFCR = (uint32_t)tmpreg1; in ETH_MACDMAConfig()
1981 tmpreg1 = (heth->Instance)->MACFCR; in ETH_MACDMAConfig()
1983 (heth->Instance)->MACFCR = tmpreg1; in ETH_MACDMAConfig()
1993 tmpreg1 = (heth->Instance)->MACVLANTR; in ETH_MACDMAConfig()
1995 (heth->Instance)->MACVLANTR = tmpreg1; in ETH_MACDMAConfig()
2016 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_MACDMAConfig()
2018 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; in ETH_MACDMAConfig()
2029 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | in ETH_MACDMAConfig()
2040 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; in ETH_MACDMAConfig()
2044 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_MACDMAConfig()
2046 (heth->Instance)->DMAOMR = tmpreg1; in ETH_MACDMAConfig()
2067 tmpreg1 = (heth->Instance)->DMABMR; in ETH_MACDMAConfig()
2069 (heth->Instance)->DMABMR = tmpreg1; in ETH_MACDMAConfig()
2096 uint32_t tmpreg1; in ETH_MACAddressConfig() local
2105 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; in ETH_MACAddressConfig()
2107 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; in ETH_MACAddressConfig()
2109 …tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) |… in ETH_MACAddressConfig()
2112 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; in ETH_MACAddressConfig()
2123 __IO uint32_t tmpreg1 = 0U; in ETH_MACTransmissionEnable() local
2130 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACTransmissionEnable()
2132 (heth->Instance)->MACCR = tmpreg1; in ETH_MACTransmissionEnable()
2143 __IO uint32_t tmpreg1 = 0U; in ETH_MACTransmissionDisable() local
2150 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACTransmissionDisable()
2152 (heth->Instance)->MACCR = tmpreg1; in ETH_MACTransmissionDisable()
2163 __IO uint32_t tmpreg1 = 0U; in ETH_MACReceptionEnable() local
2170 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACReceptionEnable()
2172 (heth->Instance)->MACCR = tmpreg1; in ETH_MACReceptionEnable()
2183 __IO uint32_t tmpreg1 = 0U; in ETH_MACReceptionDisable() local
2190 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACReceptionDisable()
2192 (heth->Instance)->MACCR = tmpreg1; in ETH_MACReceptionDisable()
2251 __IO uint32_t tmpreg1 = 0U; in ETH_FlushTransmitFIFO() local
2258 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_FlushTransmitFIFO()
2260 (heth->Instance)->DMAOMR = tmpreg1; in ETH_FlushTransmitFIFO()