Lines Matching refs:hdma
134 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…
135 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
136 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
172 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) in HAL_DMA_Init() argument
179 if(hdma == NULL) in HAL_DMA_Init()
185 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_Init()
186 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); in HAL_DMA_Init()
187 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); in HAL_DMA_Init()
188 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); in HAL_DMA_Init()
189 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); in HAL_DMA_Init()
190 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); in HAL_DMA_Init()
191 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); in HAL_DMA_Init()
192 assert_param(IS_DMA_MODE(hdma->Init.Mode)); in HAL_DMA_Init()
193 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); in HAL_DMA_Init()
194 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); in HAL_DMA_Init()
197 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) in HAL_DMA_Init()
199 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); in HAL_DMA_Init()
200 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); in HAL_DMA_Init()
201 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); in HAL_DMA_Init()
206 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Init()
209 __HAL_UNLOCK(hdma); in HAL_DMA_Init()
212 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Init()
215 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Init()
221 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Init()
224 hdma->State = HAL_DMA_STATE_TIMEOUT; in HAL_DMA_Init()
231 tmp = hdma->Instance->CR; in HAL_DMA_Init()
240 tmp |= hdma->Init.Channel | hdma->Init.Direction | in HAL_DMA_Init()
241 hdma->Init.PeriphInc | hdma->Init.MemInc | in HAL_DMA_Init()
242 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | in HAL_DMA_Init()
243 hdma->Init.Mode | hdma->Init.Priority; in HAL_DMA_Init()
246 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
249 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; in HAL_DMA_Init()
253 hdma->Instance->CR = tmp; in HAL_DMA_Init()
256 tmp = hdma->Instance->FCR; in HAL_DMA_Init()
262 tmp |= hdma->Init.FIFOMode; in HAL_DMA_Init()
265 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
268 tmp |= hdma->Init.FIFOThreshold; in HAL_DMA_Init()
272 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) in HAL_DMA_Init()
274 if (DMA_CheckFifoParam(hdma) != HAL_OK) in HAL_DMA_Init()
277 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; in HAL_DMA_Init()
280 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
288 hdma->Instance->FCR = tmp; in HAL_DMA_Init()
292 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_Init()
295 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Init()
298 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Init()
301 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
312 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) in HAL_DMA_DeInit() argument
317 if(hdma == NULL) in HAL_DMA_DeInit()
323 if(hdma->State == HAL_DMA_STATE_BUSY) in HAL_DMA_DeInit()
330 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_DeInit()
333 __HAL_DMA_DISABLE(hdma); in HAL_DMA_DeInit()
336 hdma->Instance->CR = 0U; in HAL_DMA_DeInit()
339 hdma->Instance->NDTR = 0U; in HAL_DMA_DeInit()
342 hdma->Instance->PAR = 0U; in HAL_DMA_DeInit()
345 hdma->Instance->M0AR = 0U; in HAL_DMA_DeInit()
348 hdma->Instance->M1AR = 0U; in HAL_DMA_DeInit()
351 hdma->Instance->FCR = 0x00000021U; in HAL_DMA_DeInit()
354 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_DeInit()
357 hdma->XferCpltCallback = NULL; in HAL_DMA_DeInit()
358 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_DeInit()
359 hdma->XferM1CpltCallback = NULL; in HAL_DMA_DeInit()
360 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_DeInit()
361 hdma->XferErrorCallback = NULL; in HAL_DMA_DeInit()
362 hdma->XferAbortCallback = NULL; in HAL_DMA_DeInit()
365 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_DeInit()
368 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_DeInit()
371 hdma->State = HAL_DMA_STATE_RESET; in HAL_DMA_DeInit()
374 __HAL_UNLOCK(hdma); in HAL_DMA_DeInit()
410 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, … in HAL_DMA_Start() argument
418 __HAL_LOCK(hdma); in HAL_DMA_Start()
420 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start()
423 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start()
426 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start()
429 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start()
432 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start()
437 __HAL_UNLOCK(hdma); in HAL_DMA_Start()
454 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres… in HAL_DMA_Start_IT() argument
459 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Start_IT()
465 __HAL_LOCK(hdma); in HAL_DMA_Start_IT()
467 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start_IT()
470 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start_IT()
473 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start_IT()
476 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start_IT()
479 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Start_IT()
482 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; in HAL_DMA_Start_IT()
484 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_Start_IT()
486 hdma->Instance->CR |= DMA_IT_HT; in HAL_DMA_Start_IT()
490 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start_IT()
495 __HAL_UNLOCK(hdma); in HAL_DMA_Start_IT()
516 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort() argument
519 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Abort()
523 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort()
525 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort()
528 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
535 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_Abort()
536 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
538 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_Abort()
540 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_Abort()
544 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort()
547 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Abort()
553 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Abort()
556 hdma->State = HAL_DMA_STATE_TIMEOUT; in HAL_DMA_Abort()
559 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
566 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Abort()
569 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort()
572 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
583 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort_IT() argument
585 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort_IT()
587 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort_IT()
593 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_Abort_IT()
596 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort_IT()
613 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com… in HAL_DMA_PollForTransfer() argument
623 if(HAL_DMA_STATE_BUSY != hdma->State) in HAL_DMA_PollForTransfer()
626 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_PollForTransfer()
627 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
632 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) in HAL_DMA_PollForTransfer()
634 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; in HAL_DMA_PollForTransfer()
642 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
647 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
650 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_PollForTransfer()
653 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) in HAL_DMA_PollForTransfer()
661 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_PollForTransfer()
664 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
667 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
676 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
679 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_PollForTransfer()
682 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
685 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
688 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_PollForTransfer()
691 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
694 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
697 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_PollForTransfer()
700 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
704 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_PollForTransfer()
706 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) in HAL_DMA_PollForTransfer()
708 HAL_DMA_Abort(hdma); in HAL_DMA_PollForTransfer()
711 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
714 hdma->State= HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
717 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
727 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
729 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
732 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
738 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
750 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) in HAL_DMA_IRQHandler() argument
757 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_IRQHandler()
762 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
764 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) in HAL_DMA_IRQHandler()
767 hdma->Instance->CR &= ~(DMA_IT_TE); in HAL_DMA_IRQHandler()
770 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
773 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_IRQHandler()
777 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
779 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) in HAL_DMA_IRQHandler()
782 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
785 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_IRQHandler()
789 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
791 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) in HAL_DMA_IRQHandler()
794 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
797 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_IRQHandler()
801 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
803 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) in HAL_DMA_IRQHandler()
806 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
809 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) in HAL_DMA_IRQHandler()
812 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) in HAL_DMA_IRQHandler()
814 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
817 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
823 if(hdma->XferM1HalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
826 hdma->XferM1HalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
833 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) in HAL_DMA_IRQHandler()
836 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
839 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
842 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
848 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
850 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) in HAL_DMA_IRQHandler()
853 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
855 if(HAL_DMA_STATE_ABORT == hdma->State) in HAL_DMA_IRQHandler()
858 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_IRQHandler()
859 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
861 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_IRQHandler()
863 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
867 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_IRQHandler()
870 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
873 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
875 if(hdma->XferAbortCallback != NULL) in HAL_DMA_IRQHandler()
877 hdma->XferAbortCallback(hdma); in HAL_DMA_IRQHandler()
882 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) in HAL_DMA_IRQHandler()
885 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) in HAL_DMA_IRQHandler()
887 if(hdma->XferM1CpltCallback != NULL) in HAL_DMA_IRQHandler()
890 hdma->XferM1CpltCallback(hdma); in HAL_DMA_IRQHandler()
896 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
899 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
906 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) in HAL_DMA_IRQHandler()
909 hdma->Instance->CR &= ~(DMA_IT_TC); in HAL_DMA_IRQHandler()
912 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
915 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
918 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
921 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
928 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_IRQHandler()
930 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) in HAL_DMA_IRQHandler()
932 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_IRQHandler()
935 __HAL_DMA_DISABLE(hdma); in HAL_DMA_IRQHandler()
944 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); in HAL_DMA_IRQHandler()
947 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
950 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
953 if(hdma->XferErrorCallback != NULL) in HAL_DMA_IRQHandler()
956 hdma->XferErrorCallback(hdma); in HAL_DMA_IRQHandler()
971 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb… in HAL_DMA_RegisterCallback() argument
977 __HAL_LOCK(hdma); in HAL_DMA_RegisterCallback()
979 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_RegisterCallback()
984 hdma->XferCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
988 hdma->XferHalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
992 hdma->XferM1CpltCallback = pCallback; in HAL_DMA_RegisterCallback()
996 hdma->XferM1HalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1000 hdma->XferErrorCallback = pCallback; in HAL_DMA_RegisterCallback()
1004 hdma->XferAbortCallback = pCallback; in HAL_DMA_RegisterCallback()
1020 __HAL_UNLOCK(hdma); in HAL_DMA_RegisterCallback()
1033 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal… in HAL_DMA_UnRegisterCallback() argument
1038 __HAL_LOCK(hdma); in HAL_DMA_UnRegisterCallback()
1040 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_UnRegisterCallback()
1045 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1049 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1053 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1057 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1061 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1065 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1069 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1070 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1071 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1072 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1073 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1074 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1088 __HAL_UNLOCK(hdma); in HAL_DMA_UnRegisterCallback()
1118 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) in HAL_DMA_GetState() argument
1120 return hdma->State; in HAL_DMA_GetState()
1129 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) in HAL_DMA_GetError() argument
1131 return hdma->ErrorCode; in HAL_DMA_GetError()
1155 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32… in DMA_SetConfig() argument
1158 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); in DMA_SetConfig()
1161 hdma->Instance->NDTR = DataLength; in DMA_SetConfig()
1164 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) in DMA_SetConfig()
1167 hdma->Instance->PAR = DstAddress; in DMA_SetConfig()
1170 hdma->Instance->M0AR = SrcAddress; in DMA_SetConfig()
1176 hdma->Instance->PAR = SrcAddress; in DMA_SetConfig()
1179 hdma->Instance->M0AR = DstAddress; in DMA_SetConfig()
1189 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) in DMA_CalcBaseAndBitshift() argument
1191 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; in DMA_CalcBaseAndBitshift()
1195 hdma->StreamIndex = flagBitshiftOffset[stream_number]; in DMA_CalcBaseAndBitshift()
1200 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); in DMA_CalcBaseAndBitshift()
1205 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); in DMA_CalcBaseAndBitshift()
1208 return hdma->StreamBaseAddress; in DMA_CalcBaseAndBitshift()
1217 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) in DMA_CheckFifoParam() argument
1220 uint32_t tmp = hdma->Init.FIFOThreshold; in DMA_CheckFifoParam()
1223 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) in DMA_CheckFifoParam()
1229 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1235 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1248 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) in DMA_CheckFifoParam()
1257 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1263 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1284 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()