295   regs->IFCR = 0x3FU << hdma->StreamIndex;  in HAL_DMA_Init()
365   regs->IFCR = 0x3FU << hdma->StreamIndex;  in HAL_DMA_DeInit()
479     regs->IFCR = 0x3FU << hdma->StreamIndex;  in HAL_DMA_Start_IT()
566     regs->IFCR = 0x3FU << hdma->StreamIndex;  in HAL_DMA_Abort()
642     mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
647     mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
676     if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_PollForTransfer()
682       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
685     if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_PollForTransfer()
691       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
694     if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_PollForTransfer()
700       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
711       regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
727     regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
738     regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;  in HAL_DMA_PollForTransfer()
762   if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_IRQHandler()
770       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;  in HAL_DMA_IRQHandler()
777   if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_IRQHandler()
782       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;  in HAL_DMA_IRQHandler()
789   if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_IRQHandler()
794       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;  in HAL_DMA_IRQHandler()
801   if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_IRQHandler()
806       regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;  in HAL_DMA_IRQHandler()
848   if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)  in HAL_DMA_IRQHandler()
853       regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;  in HAL_DMA_IRQHandler()
867         regs->IFCR = 0x3FU << hdma->StreamIndex;  in HAL_DMA_IRQHandler()
1195   hdma->StreamIndex = flagBitshiftOffset[stream_number];  in DMA_CalcBaseAndBitshift()