Lines Matching refs:APB2ENR

910                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
912                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
917                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
919                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
924                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
926                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
931                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
933                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
938                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
940                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
945                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
947                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
952                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
954                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
959                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
961                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
966                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
968                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
973                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
975                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
981                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
983                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
988                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
990                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
995                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
997                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1000 #define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
1001 #define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1002 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1003 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
1004 #define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
1005 #define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1006 #define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1007 #define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
1008 #define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
1009 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
1010 #define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
1011 #define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1012 #define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
1024 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET)
1025 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET)
1026 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET)
1027 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET)
1028 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET)
1029 #define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET)
1030 #define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET)
1031 #define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET)
1032 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET)
1033 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET)
1034 #define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET)
1035 #define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET)
1036 #define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET)
1038 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET)
1039 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET)
1040 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET)
1041 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET)
1042 #define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET)
1043 #define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET)
1044 #define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET)
1045 #define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET)
1046 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET)
1047 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET)
1048 #define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET)
1049 #define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET)
1050 #define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET)