Lines Matching refs:AHBPERIPH_BASE
745 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) macro
793 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
794 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
795 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
796 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
797 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
798 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
799 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
800 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
801 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)
802 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)
803 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)
804 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)
805 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)
806 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)
807 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
808 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
810 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */