Lines Matching refs:AHBPERIPH_BASE
599 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) macro
635 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
636 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
637 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
638 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
639 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
640 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
641 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
642 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
643 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)
644 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)
645 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)
646 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)
647 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)
648 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)
649 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
650 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
652 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */