530   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
536   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
563   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
617   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
626   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
667   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
771   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
774   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
824   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
850   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
853   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
903   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
929   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
932   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
982   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1008   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1011   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1049   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1072   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1080   MODIFY_REG(TIMx->CCER,  in IC1Config()
1105   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1113   MODIFY_REG(TIMx->CCER,  in IC2Config()
1138   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1146   MODIFY_REG(TIMx->CCER,  in IC3Config()
1171   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1179   MODIFY_REG(TIMx->CCER,  in IC4Config()