208 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_Init()  argument
216   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_Init()
233   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FSMC_NORSRAM_Init()
278   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FSMC_NORSRAM_Init()
291 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_DeInit()  argument
295   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_DeInit()
300   __FSMC_NORSRAM_DISABLE(Device, Bank);  in FSMC_NORSRAM_DeInit()
306     Device->BTCR[Bank] = 0x000030DBU;  in FSMC_NORSRAM_DeInit()
311     Device->BTCR[Bank] = 0x000030D2U;  in FSMC_NORSRAM_DeInit()
314   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
328 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_Timing_Init()  argument
333   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_Timing_Init()
344   Device->BTCR[Bank + 1U] =  in FSMC_NORSRAM_Timing_Init()
368 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,  in FSMC_NORSRAM_Extended_Timing_Init()  argument
379     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));  in FSMC_NORSRAM_Extended_Timing_Init()
394 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
400 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
410     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FSMC_NORSRAM_Extended_Timing_Init()
440 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Enable()  argument
443   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_WriteOperation_Enable()
447   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Enable()
458 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Disable()  argument
461   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_WriteOperation_Disable()
465   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Disable()
530 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init)  in FSMC_NAND_Init()  argument
533   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_Init()
546 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FSMC_NAND_Init()
557 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FSMC_NAND_Init()
577 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,  in FSMC_NAND_CommonSpace_Timing_Init()  argument
581   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_CommonSpace_Timing_Init()
592 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_CommonSpace_Timing_Init()
600 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_CommonSpace_Timing_Init()
617 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,  in FSMC_NAND_AttributeSpace_Timing_Init()  argument
621   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_AttributeSpace_Timing_Init()
632 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_AttributeSpace_Timing_Init()
640 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_AttributeSpace_Timing_Init()
655 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_DeInit()  argument
658   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_DeInit()
662   __FSMC_NAND_DISABLE(Device, Bank);  in FSMC_NAND_DeInit()
668     WRITE_REG(Device->PCR2,  0x00000018U);  in FSMC_NAND_DeInit()
669     WRITE_REG(Device->SR2,   0x00000040U);  in FSMC_NAND_DeInit()
670     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
671     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
677     WRITE_REG(Device->PCR3,  0x00000018U);  in FSMC_NAND_DeInit()
678     WRITE_REG(Device->SR3,   0x00000040U);  in FSMC_NAND_DeInit()
679     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
680     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
712 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Enable()  argument
715   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_ECC_Enable()
721     SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);  in FSMC_NAND_ECC_Enable()
725     SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);  in FSMC_NAND_ECC_Enable()
738 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Disable()  argument
741   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_ECC_Disable()
747     CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);  in FSMC_NAND_ECC_Disable()
751     CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);  in FSMC_NAND_ECC_Disable()
765 HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FSMC_NAND_GetECC()  argument
771   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_GetECC()
778   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)  in FSMC_NAND_GetECC()
793     *ECCval = (uint32_t)Device->ECCR2;  in FSMC_NAND_GetECC()
798     *ECCval = (uint32_t)Device->ECCR3;  in FSMC_NAND_GetECC()
858 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init)  in FSMC_PCCARD_Init()  argument
861   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_Init()
869   MODIFY_REG(Device->PCR4,  in FSMC_PCCARD_Init()
891 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_CommonSpace_Timing_Init()  argument
895   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_CommonSpace_Timing_Init()
904   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,  in FSMC_PCCARD_CommonSpace_Timing_Init()
920 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_AttributeSpace_Timing_Init()  argument
924   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_AttributeSpace_Timing_Init()
933   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,  in FSMC_PCCARD_AttributeSpace_Timing_Init()
949 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_IOSpace_Timing_Init()  argument
953   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_IOSpace_Timing_Init()
962   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,  in FSMC_PCCARD_IOSpace_Timing_Init()
976 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)  in FSMC_PCCARD_DeInit()  argument
979   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_DeInit()
982   __FSMC_PCCARD_DISABLE(Device);  in FSMC_PCCARD_DeInit()
985   Device->PCR4    = 0x00000018U;  in FSMC_PCCARD_DeInit()
986   Device->SR4     = 0x00000040U;  in FSMC_PCCARD_DeInit()
987   Device->PMEM4   = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()
988   Device->PATT4   = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()
989   Device->PIO4    = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()