Lines Matching refs:CFGR

226   CLEAR_REG(RCC->CFGR);  in HAL_RCC_DeInit()
229 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) in HAL_RCC_DeInit()
262 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
775 pll_config = RCC->CFGR; in HAL_RCC_OscConfig()
852 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); in HAL_RCC_ClockConfig()
857 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); in HAL_RCC_ClockConfig()
862 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
931 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
938 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); in HAL_RCC_ClockConfig()
942 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CF… in HAL_RCC_ClockConfig()
1100 tmpreg = RCC->CFGR; in HAL_RCC_GetSysClockFreq()
1118 … prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; in HAL_RCC_GetSysClockFreq()
1188 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]… in HAL_RCC_GetPCLK1Freq()
1200 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]… in HAL_RCC_GetPCLK2Freq()
1285 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); in HAL_RCC_GetOscConfig()
1286 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL); in HAL_RCC_GetOscConfig()
1320 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); in HAL_RCC_GetClockConfig()
1323 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); in HAL_RCC_GetClockConfig()
1326 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); in HAL_RCC_GetClockConfig()
1329 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); in HAL_RCC_GetClockConfig()