Lines Matching refs:tmpreg1
214 uint32_t tmpreg1 = 0U, phyreg = 0U; in HAL_ETH_Init() local
282 tmpreg1 = (heth->Instance)->MACMIIAR; in HAL_ETH_Init()
284 tmpreg1 &= ETH_MACMIIAR_CR_MASK; in HAL_ETH_Init()
293 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16; in HAL_ETH_Init()
298 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26; in HAL_ETH_Init()
303 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42; in HAL_ETH_Init()
307 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; in HAL_ETH_Init()
1285 uint32_t tmpreg1 = 0U; in HAL_ETH_ReadPHYRegister() local
1300 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_ReadPHYRegister()
1303 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; in HAL_ETH_ReadPHYRegister()
1306 …tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device add… in HAL_ETH_ReadPHYRegister()
1307 …tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register ad… in HAL_ETH_ReadPHYRegister()
1308 …tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode … in HAL_ETH_ReadPHYRegister()
1309 …tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit … in HAL_ETH_ReadPHYRegister()
1312 heth->Instance->MACMIIAR = tmpreg1; in HAL_ETH_ReadPHYRegister()
1318 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) in HAL_ETH_ReadPHYRegister()
1331 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_ReadPHYRegister()
1357 uint32_t tmpreg1 = 0U; in HAL_ETH_WritePHYRegister() local
1372 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_WritePHYRegister()
1375 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; in HAL_ETH_WritePHYRegister()
1378 …tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device add… in HAL_ETH_WritePHYRegister()
1379 …tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register addr… in HAL_ETH_WritePHYRegister()
1380 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ in HAL_ETH_WritePHYRegister()
1381 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ in HAL_ETH_WritePHYRegister()
1387 heth->Instance->MACMIIAR = tmpreg1; in HAL_ETH_WritePHYRegister()
1393 while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) in HAL_ETH_WritePHYRegister()
1406 tmpreg1 = heth->Instance->MACMIIAR; in HAL_ETH_WritePHYRegister()
1528 uint32_t tmpreg1 = 0U; in HAL_ETH_ConfigMAC() local
1572 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1574 tmpreg1 &= ETH_MACCR_CLEAR_MASK; in HAL_ETH_ConfigMAC()
1576 tmpreg1 |= (uint32_t)(macconf->Watchdog | in HAL_ETH_ConfigMAC()
1591 (heth->Instance)->MACCR = (uint32_t)tmpreg1; in HAL_ETH_ConfigMAC()
1595 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1597 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_ConfigMAC()
1612 tmpreg1 = (heth->Instance)->MACFFR; in HAL_ETH_ConfigMAC()
1614 (heth->Instance)->MACFFR = tmpreg1; in HAL_ETH_ConfigMAC()
1625 tmpreg1 = (heth->Instance)->MACFCR; in HAL_ETH_ConfigMAC()
1627 tmpreg1 &= ETH_MACFCR_CLEAR_MASK; in HAL_ETH_ConfigMAC()
1629 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | in HAL_ETH_ConfigMAC()
1637 (heth->Instance)->MACFCR = (uint32_t)tmpreg1; in HAL_ETH_ConfigMAC()
1641 tmpreg1 = (heth->Instance)->MACFCR; in HAL_ETH_ConfigMAC()
1643 (heth->Instance)->MACFCR = tmpreg1; in HAL_ETH_ConfigMAC()
1651 tmpreg1 = (heth->Instance)->MACVLANTR; in HAL_ETH_ConfigMAC()
1653 (heth->Instance)->MACVLANTR = tmpreg1; in HAL_ETH_ConfigMAC()
1659 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1662 tmpreg1 &= ~(0x00004800U); in HAL_ETH_ConfigMAC()
1664 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); in HAL_ETH_ConfigMAC()
1667 (heth->Instance)->MACCR = (uint32_t)tmpreg1; in HAL_ETH_ConfigMAC()
1671 tmpreg1 = (heth->Instance)->MACCR; in HAL_ETH_ConfigMAC()
1673 (heth->Instance)->MACCR = tmpreg1; in HAL_ETH_ConfigMAC()
1695 uint32_t tmpreg1 = 0U; in HAL_ETH_ConfigDMA() local
1722 tmpreg1 = (heth->Instance)->DMAOMR; in HAL_ETH_ConfigDMA()
1724 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; in HAL_ETH_ConfigDMA()
1726 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | in HAL_ETH_ConfigDMA()
1737 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; in HAL_ETH_ConfigDMA()
1741 tmpreg1 = (heth->Instance)->DMAOMR; in HAL_ETH_ConfigDMA()
1743 (heth->Instance)->DMAOMR = tmpreg1; in HAL_ETH_ConfigDMA()
1756 tmpreg1 = (heth->Instance)->DMABMR; in HAL_ETH_ConfigDMA()
1758 (heth->Instance)->DMABMR = tmpreg1; in HAL_ETH_ConfigDMA()
1827 uint32_t tmpreg1 = 0U; in ETH_MACDMAConfig() local
1878 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACDMAConfig()
1880 tmpreg1 &= ETH_MACCR_CLEAR_MASK; in ETH_MACDMAConfig()
1894 tmpreg1 |= (uint32_t)(macinit.Watchdog | in ETH_MACDMAConfig()
1909 (heth->Instance)->MACCR = (uint32_t)tmpreg1; in ETH_MACDMAConfig()
1913 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACDMAConfig()
1915 (heth->Instance)->MACCR = tmpreg1; in ETH_MACDMAConfig()
1938 tmpreg1 = (heth->Instance)->MACFFR; in ETH_MACDMAConfig()
1940 (heth->Instance)->MACFFR = tmpreg1; in ETH_MACDMAConfig()
1951 tmpreg1 = (heth->Instance)->MACFCR; in ETH_MACDMAConfig()
1953 tmpreg1 &= ETH_MACFCR_CLEAR_MASK; in ETH_MACDMAConfig()
1961 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | in ETH_MACDMAConfig()
1969 (heth->Instance)->MACFCR = (uint32_t)tmpreg1; in ETH_MACDMAConfig()
1973 tmpreg1 = (heth->Instance)->MACFCR; in ETH_MACDMAConfig()
1975 (heth->Instance)->MACFCR = tmpreg1; in ETH_MACDMAConfig()
1985 tmpreg1 = (heth->Instance)->MACVLANTR; in ETH_MACDMAConfig()
1987 (heth->Instance)->MACVLANTR = tmpreg1; in ETH_MACDMAConfig()
2007 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_MACDMAConfig()
2009 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; in ETH_MACDMAConfig()
2020 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | in ETH_MACDMAConfig()
2031 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; in ETH_MACDMAConfig()
2035 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_MACDMAConfig()
2037 (heth->Instance)->DMAOMR = tmpreg1; in ETH_MACDMAConfig()
2056 tmpreg1 = (heth->Instance)->DMABMR; in ETH_MACDMAConfig()
2058 (heth->Instance)->DMABMR = tmpreg1; in ETH_MACDMAConfig()
2085 uint32_t tmpreg1; in ETH_MACAddressConfig() local
2094 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; in ETH_MACAddressConfig()
2096 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; in ETH_MACAddressConfig()
2098 …tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) |… in ETH_MACAddressConfig()
2101 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; in ETH_MACAddressConfig()
2112 __IO uint32_t tmpreg1 = 0U; in ETH_MACTransmissionEnable() local
2119 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACTransmissionEnable()
2121 (heth->Instance)->MACCR = tmpreg1; in ETH_MACTransmissionEnable()
2132 __IO uint32_t tmpreg1 = 0U; in ETH_MACTransmissionDisable() local
2139 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACTransmissionDisable()
2141 (heth->Instance)->MACCR = tmpreg1; in ETH_MACTransmissionDisable()
2152 __IO uint32_t tmpreg1 = 0U; in ETH_MACReceptionEnable() local
2159 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACReceptionEnable()
2161 (heth->Instance)->MACCR = tmpreg1; in ETH_MACReceptionEnable()
2172 __IO uint32_t tmpreg1 = 0U; in ETH_MACReceptionDisable() local
2179 tmpreg1 = (heth->Instance)->MACCR; in ETH_MACReceptionDisable()
2181 (heth->Instance)->MACCR = tmpreg1; in ETH_MACReceptionDisable()
2240 __IO uint32_t tmpreg1 = 0U; in ETH_FlushTransmitFIFO() local
2247 tmpreg1 = (heth->Instance)->DMAOMR; in ETH_FlushTransmitFIFO()
2249 (heth->Instance)->DMAOMR = tmpreg1; in ETH_FlushTransmitFIFO()