489   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
495   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
522   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
578   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
587   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
628   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
732   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
735   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
785   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
811   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
814   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
864   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
890   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
893   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
943   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
969   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
972   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1010   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1033   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1041   MODIFY_REG(TIMx->CCER,  in IC1Config()
1066   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1074   MODIFY_REG(TIMx->CCER,  in IC2Config()
1099   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1107   MODIFY_REG(TIMx->CCER,  in IC3Config()
1132   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1140   MODIFY_REG(TIMx->CCER,  in IC4Config()