585   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
600   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
612   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
615   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
638   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
769   uint32_t tmpcr2;  in OC1Config()  local
784   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
815     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
818     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
822   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
848   uint32_t tmpcr2;  in OC2Config()  local
863   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
894     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
897     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
901   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
927   uint32_t tmpcr2;  in OC3Config()  local
942   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
973     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
976     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
980   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1006   uint32_t tmpcr2;  in OC4Config()  local
1021   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1043     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1047   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()