Lines Matching refs:CCER
508 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
514 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
541 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
597 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
606 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
647 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
778 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
781 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
831 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
857 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
860 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
910 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
936 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
939 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
989 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
1015 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); in OC4Config()
1018 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
1056 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1083 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); in OC5Config()
1086 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1117 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1144 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); in OC6Config()
1147 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1177 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()
1200 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; in IC1Config()
1208 MODIFY_REG(TIMx->CCER, in IC1Config()
1233 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; in IC2Config()
1241 MODIFY_REG(TIMx->CCER, in IC2Config()
1266 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; in IC3Config()
1274 MODIFY_REG(TIMx->CCER, in IC3Config()
1299 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; in IC4Config()
1307 MODIFY_REG(TIMx->CCER, in IC4Config()