Lines Matching refs:AHB1PERIPH_BASE
733 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) macro
781 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)
782 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008UL)
783 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001CUL)
784 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030UL)
785 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044UL)
786 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058UL)
787 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006CUL)
788 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080UL)
789 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400UL)
790 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408UL)
791 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041CUL)
792 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430UL)
793 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444UL)
794 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458UL)
795 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000UL)
796 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
800 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)
801 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000UL)