25   * If no LICENSE file comes with this software, it is provided AS-IS.
37         (++) Enable QuadSPI clock interface with __HAL_RCC_QUADSPI_CLK_ENABLE().
38 …(++) Reset QuadSPI Peripheral with __HAL_RCC_QUADSPI_FORCE_RESET() and __HAL_RCC_QUADSPI_RELEASE_R…
39         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
42             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
44             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
45             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
46             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
979       /* Configure QSPI: CCR register with functional as indirect write */  in HAL_QSPI_Transmit()
1063       /* Configure QSPI: CCR register with functional as indirect read */  in HAL_QSPI_Receive()
1118   * @brief  Send an amount of data in non-blocking mode with interrupt.
1148       /* Configure QSPI: CCR register with functional as indirect write */  in HAL_QSPI_Transmit_IT()
1178   * @brief  Receive an amount of data in non-blocking mode with interrupt.
1209       /* Configure QSPI: CCR register with functional as indirect read */  in HAL_QSPI_Receive_IT()
1242   * @brief  Send an amount of data in non-blocking mode with DMA.
1277           => no transfer possible with DMA peripheral access configured as halfword */  in HAL_QSPI_Transmit_DMA()
1294           => no transfer possible with DMA peripheral access configured as word */  in HAL_QSPI_Transmit_DMA()
1323         /* Configure QSPI: CCR register with functional mode as indirect write */  in HAL_QSPI_Transmit_DMA()
1386   * @brief  Receive an amount of data in non-blocking mode with DMA.
1422              => no transfer possible with DMA peripheral access configured as halfword */  in HAL_QSPI_Receive_DMA()
1439              => no transfer possible with DMA peripheral access configured as word */  in HAL_QSPI_Receive_DMA()
1487           /* Configure QSPI: CCR register with functional as indirect read */  in HAL_QSPI_Receive_DMA()
1591       /* Configure QSPI: PSMAR register with the status match value */  in HAL_QSPI_AutoPolling()
1594       /* Configure QSPI: PSMKR register with the status mask value */  in HAL_QSPI_AutoPolling()
1597       /* Configure QSPI: PIR register with the interval value */  in HAL_QSPI_AutoPolling()
1600       /* Configure QSPI: CR register with Match mode and Automatic stop enabled  in HAL_QSPI_AutoPolling()
1691       /* Configure QSPI: PSMAR register with the status match value */  in HAL_QSPI_AutoPolling_IT()
1694       /* Configure QSPI: PSMKR register with the status mask value */  in HAL_QSPI_AutoPolling_IT()
1697       /* Configure QSPI: PIR register with the interval value */  in HAL_QSPI_AutoPolling_IT()
1700       /* Configure QSPI: CR register with Match mode and Automatic stop mode */  in HAL_QSPI_AutoPolling_IT()
1791       /* Configure QSPI: CR register with timeout counter enable */  in HAL_QSPI_MemoryMapped()
1798         /* Configure QSPI: LPTR register with the low-power timeout value */  in HAL_QSPI_MemoryMapped()
2269       /* Configure QSPI: CR register with Abort request */  in HAL_QSPI_Abort()
2353         /* Configure QSPI: CR register with Abort request */  in HAL_QSPI_Abort_IT()
2390     /* Synchronize init structure with new FIFO threshold value */  in HAL_QSPI_SetFifoThreshold()
2532     /* Configure QSPI: CR register with Abort request */  in QSPI_DMAAbortCplt()
2598     /* Configure QSPI: DLR register with the number of data to read or write */  in QSPI_Config()
2606       /* Configure QSPI: ABR register with alternate bytes value */  in QSPI_Config()
2611         /*---- Command with instruction, address and alternate bytes ----*/  in QSPI_Config()
2612         /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()
2621           /* Configure QSPI: AR register with address value */  in QSPI_Config()
2627         /*---- Command with instruction and alternate bytes ----*/  in QSPI_Config()
2628         /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()
2640         /*---- Command with instruction and address ----*/  in QSPI_Config()
2641         /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()
2649           /* Configure QSPI: AR register with address value */  in QSPI_Config()
2655         /*---- Command with only instruction ----*/  in QSPI_Config()
2656         /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()
2668       /* Configure QSPI: ABR register with alternate bytes value */  in QSPI_Config()
2673         /*---- Command with address and alternate bytes ----*/  in QSPI_Config()
2674         /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()
2683           /* Configure QSPI: AR register with address value */  in QSPI_Config()
2689         /*---- Command with only alternate bytes ----*/  in QSPI_Config()
2690         /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()
2701         /*---- Command with only address ----*/  in QSPI_Config()
2702         /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()
2710           /* Configure QSPI: AR register with address value */  in QSPI_Config()
2716         /*---- Command with only data phase ----*/  in QSPI_Config()
2719           /* Configure QSPI: CCR register with all communications parameters */  in QSPI_Config()