174                                     FMC_NORSRAM_InitTypeDef *Init)  in FMC_NORSRAM_Init()  argument
182   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));  in FMC_NORSRAM_Init()
183   assert_param(IS_FMC_MUX(Init->DataAddressMux));  in FMC_NORSRAM_Init()
184   assert_param(IS_FMC_MEMORY(Init->MemoryType));  in FMC_NORSRAM_Init()
185   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));  in FMC_NORSRAM_Init()
186   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));  in FMC_NORSRAM_Init()
187   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));  in FMC_NORSRAM_Init()
188   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));  in FMC_NORSRAM_Init()
189   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));  in FMC_NORSRAM_Init()
190   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));  in FMC_NORSRAM_Init()
191   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));  in FMC_NORSRAM_Init()
192   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));  in FMC_NORSRAM_Init()
193   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));  in FMC_NORSRAM_Init()
194   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));  in FMC_NORSRAM_Init()
195   assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));  in FMC_NORSRAM_Init()
196   assert_param(IS_FMC_PAGESIZE(Init->PageSize));  in FMC_NORSRAM_Init()
197   assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));  in FMC_NORSRAM_Init()
198   assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse));  in FMC_NORSRAM_Init()
201   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
204   if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)  in FMC_NORSRAM_Init()
214               Init->DataAddressMux          | \  in FMC_NORSRAM_Init()
215               Init->MemoryType              | \  in FMC_NORSRAM_Init()
216               Init->MemoryDataWidth         | \  in FMC_NORSRAM_Init()
217               Init->BurstAccessMode         | \  in FMC_NORSRAM_Init()
218               Init->WaitSignalPolarity      | \  in FMC_NORSRAM_Init()
219               Init->WaitSignalActive        | \  in FMC_NORSRAM_Init()
220               Init->WriteOperation          | \  in FMC_NORSRAM_Init()
221               Init->WaitSignal              | \  in FMC_NORSRAM_Init()
222               Init->ExtendedMode            | \  in FMC_NORSRAM_Init()
223               Init->AsynchronousWait        | \  in FMC_NORSRAM_Init()
224               Init->WriteBurst);  in FMC_NORSRAM_Init()
226   btcr_reg |= Init->ContinuousClock;  in FMC_NORSRAM_Init()
227   btcr_reg |= Init->WriteFifo;  in FMC_NORSRAM_Init()
228   btcr_reg |= Init->NBLSetupTime;  in FMC_NORSRAM_Init()
229   btcr_reg |= Init->PageSize;  in FMC_NORSRAM_Init()
250   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FMC_NORSRAM_Init()
253 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN…  in FMC_NORSRAM_Init()
255     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
258   if (Init->NSBank != FMC_NORSRAM_BANK1)  in FMC_NORSRAM_Init()
261     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));  in FMC_NORSRAM_Init()
265   if (Init->MaxChipSelectPulse == ENABLE)  in FMC_NORSRAM_Init()
268     assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime));  in FMC_NORSRAM_Init()
271     MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));  in FMC_NORSRAM_Init()
274     switch (Init->NSBank)  in FMC_NORSRAM_Init()
559 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)  in FMC_NAND_Init()  argument
563   assert_param(IS_FMC_NAND_BANK(Init->NandBank));  in FMC_NAND_Init()
564   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));  in FMC_NAND_Init()
565   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));  in FMC_NAND_Init()
566   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));  in FMC_NAND_Init()
567   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));  in FMC_NAND_Init()
568   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));  in FMC_NAND_Init()
569   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));  in FMC_NAND_Init()
572   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |  in FMC_NAND_Init()
574                                            Init->MemoryDataWidth                        |  in FMC_NAND_Init()
575                                            Init->EccComputation                         |  in FMC_NAND_Init()
576                                            Init->ECCPageSize                            |  in FMC_NAND_Init()
577                                            ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos)  |  in FMC_NAND_Init()
578                                            ((Init->TARSetupTime)  << FMC_PCR_TAR_Pos)));  in FMC_NAND_Init()