Lines Matching full:with
20 * If no LICENSE file comes with this software, it is provided AS-IS.
80 with the right parameter to configure the wake up pin polarity (Low or
199 * The prototype is kept just to maintain compatibility with other
300 (++) PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction.
301 (++) PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction.
304 kept as parameter just to maintain compatibility with other families.
314 The Stop 0 mode is based on the Cortex-M33 Deepsleep mode combined with
318 Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
326 with :
329 (+++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction.
330 (+++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction.
333 kept as parameter just to maintain compatibility with other families.
338 can be external interrupts or peripherals with wakeup capability.
346 The Standby mode is used to achieve the lowest power consumption with BOR.
351 The RTC can remain active (Standby mode with RTC, Standby mode without
355 I/O with internal pull-up, internal pull-down or floating.
359 Standby mode, supplied by the low-power regulator (Standby with RAM2
460 * wake up source with high polarity detection and the wake
463 * param select the wake up line, the wake up source with
466 * the wake up line, the wake up source with
521 * The parameter is kept just to maintain compatibility with other
523 * @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE
526 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep mode with Wait
528 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep mode with Wait
562 * allowing a very fast wakeup time but with much higher consumption
578 * The parameter is kept just to maintain compatibility with other
580 * @param StopEntry : Specifies if Stop mode is entered with WFI or WFE
583 * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
585 * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
623 * with BOR. The internal regulator is switched off so that the VCORE
630 * regulator (Standby with RAM2 retention mode) through
633 * software : I/O with internal pull-up through
771 (++) The secured bits are not written (WI) with a non-secure write access.
772 (++) The secured bits are read as 0 (RAZ) with a non-secure read access.
779 By default, after a reset, all PWR registers can be read or written with
781 written with privileged access only. PWR_PRIVCFGR can be read by secure
783 The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access
787 (++) The PWR secure bits can be written only with privileged access,
789 (++) The PWR secure bits can be read only with privileged access except
795 The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only,
801 written only with privileged access.
803 only with privileged access except PWR_PRIVCFGR that can be read by
806 and PWR_WUSR, can be read with privileged or unprivileged accesses.