Lines Matching full:with
14 * If no LICENSE file comes with this software, it is provided AS-IS.
172 … for compatibility with some ADC on other STM32
176 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
189 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
207 … compatibility with some ADC on other STM32 families
211 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
219 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
268 … ADC_CHANNEL_ID_NUMBER_MASK with
272 … contain channels with a restricted
357 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP0" register */
358 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP1" register */
359 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP2" register */
360 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP3" register */
361 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP4" register */
362 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP5" register */
363 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP6" register */
364 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP7" register */
365 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP8" register */
366 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP9" register */
367 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP10" register */
368 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP11" register */
369 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP12" register */
370 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP13" register */
371 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP14" register */
372 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP15" register */
373 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP16" register */
374 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP17" register */
375 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP18" register */
376 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP19" register */
377 #define ADC_CHANNEL_20_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP20" register */
378 #define ADC_CHANNEL_21_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP21" register */
379 #define ADC_CHANNEL_22_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP22" register */
380 #define ADC_CHANNEL_23_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP23" register */
480 … | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs":
490 …L_VREF (3000UL) /* Analog voltage reference (Vref+) value with which
512 …NSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with
526 * @brief Driver macro reserved for internal use: isolate bits with the
576 or multimode (for devices with several ADC instances).
610 * (setting possible with ADC enabled without conversion on going,
611 * ADC enabled with conversion on going, ...)
612 * Each feature can be updated afterwards with a unitary function
613 * and potentially with ADC in a different state than disabled,
624 …uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or wi…
644 * (functions with prefix "REG").
651 * (setting possible with ADC enabled without conversion on going,
652 * ADC enabled with conversion on going, ...)
653 * Each feature can be updated afterwards with a unitary function
654 * and potentially with ADC in a different state than disabled,
665 … compatibility with some ADC on other STM32 families having this
720 * (functions with prefix "INJ").
727 * (setting possible with ADC enabled without conversion on going,
728 * ADC enabled with conversion on going, ...)
729 * Each feature can be updated afterwards with a unitary function
730 * and potentially with ADC in a different state than disabled,
741 … compatibility with some ADC on other STM32 families having this
781 * @brief Flags defines which can be used with LL_ADC_ReadReg function
838 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
862 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
865 /* List of ADC registers intended to be used (most commonly) with */
869 … (corresponding to register DR) to be used with ADC
876 … (corresponding to register CDR) to be used with
878 … with several ADC instances). Without DMA transfer,
892 … with prescaler division
895 … with prescaler division
898 … with prescaler division
901 … with prescaler division
904 … with prescaler division
907 … with prescaler division
910 … with prescaler division
913 … with prescaler division
916 … with prescaler division
919 … with prescaler division
922 … with prescaler division
955 … For devices with differential mode
962 … For devices with differential mode
970 … clock cycles. For devices with
1008 … post-processing when applied with ADC4) */
1056 …en necessary (when previous ADC conversion data is read). See description with function @ref LL_AD…
1065 … (with startup time between trigger and start of sampling). See description with function @ref LL_…
1294 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
1295 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
1304 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
1305 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
1332 … ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequ…
1333 … ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequ…
1334 … ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequ…
1335 …_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequ…
1336 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequ…
1337 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequ…
1338 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequ…
1339 … ) /*!< ADC group regular sequencer enable with 9 ranks in the sequ…
1340 … | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the seq…
1341 … | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the seq…
1342 … | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the seq…
1343 …_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the seq…
1344 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the seq…
1345 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the seq…
1346 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the seq…
1354 …LE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequ…
1355 …LE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequ…
1356 …LE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequ…
1357 …LE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequ…
1358 …LE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequ…
1359 …LE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequ…
1360 …LE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequ…
1369 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1370 … /*!< ADC group regular sequencer discontinuous mode enabled with sequence interrupti…
1371 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1372 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1373 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1374 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1375 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1377 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1385 …ber to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in…
1386 …mber to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in…
1473 …njected conversion trigger from ADC group regular. Setting compliant only with group injected trig…
1498 … ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequ…
1499 … (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequ…
1500 … (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequ…
1509 …_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interrupti…
1854 … /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (…
1865 …ar conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA …
2019 * number is returned, either defined with number
2020 * or with bitfield (only one bit must be set).
2105 * comparison with internal channel parameter to be done
2133 * number in ADC registers. The differentiation is made only with
2259 * number in ADC registers. The differentiation is made only with
2312 * define a single channel to monitor with analog watchdog
2314 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2354 * comparison with internal channel parameter to be done
2458 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
2459 * Example, with a ADC resolution of 8 bits, to set the value of
2492 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2493 * Example, with a ADC resolution of 8 bits, to get the value of
2523 * @brief Helper macro to set the ADC calibration value with both single ended
2525 * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
2541 * or ADC slave from raw value with both ADC conversion data concatenated.
2544 * In this case the transferred data need to processed with this macro
2560 * @note In case of device with multimode available and a mix of
2561 * ADC instances compliant and not compliant with multimode feature,
2562 * ADC instances not compliant with multimode feature are
2579 * - Multimode (for devices with several ADC instances)
2595 * @note This check is required by functions with setting conditioned to
2599 * @note On devices with only 1 ADC common instance, parameter of this macro
2601 * with devices featuring several ADC common instances).
2726 * On devices with small package, the pin Vref+ is not present
2765 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2828 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2835 * of the current device has characteristics in line with
2909 * intended to be used (most commonly) with DMA transfer.
2913 * @note This macro is intended to be used with LL DMA driver, refer to
2921 * @note For devices with several ADC: in multimode, some devices
2933 * (1) Available on devices with several ADC instances.
2957 * intended to be used (most commonly) with DMA transfer.
2961 * @note This macro is intended to be used with LL DMA driver, refer to
2969 * @note For devices with several ADC: in multimode, some devices
3007 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3080 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3110 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3150 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3202 * or differential (for devices with differential mode available).
3206 * @note For devices with differential mode available:
3255 * or differential (for devices with differential mode available).
3258 * @note For devices with differential mode available:
3271 /* Retrieve bits with position in register depending on parameter */ in LL_ADC_GetCalibrationOffsetFactor()
3273 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ in LL_ADC_GetCalibrationOffsetFactor()
3467 * - It is not recommended to use with interruption or DMA
3473 * - Do use with polling: 1. Start conversion,
3482 * (with startup time between trigger and start of sampling).
3483 * This feature can be combined with low power mode "auto wait".
3484 * @note With ADC low power mode "auto wait", the ADC conversion data read
3531 * - It is not recommended to use with interruption or DMA
3537 * - Do use with polling: 1. Start conversion,
3546 * (with startup time between trigger and start of sampling).
3547 * This feature can be combined with low power mode "auto wait".
3548 * @note With ADC low power mode "auto wait", the ADC conversion data read
3587 * with the lowest value is considered for the subtraction.
3666 * with parts of literals LL_ADC_CHANNEL_x or using
3671 * process the returned value with the helper macro
3719 * comparison with internal channel parameter to be done
3921 * 1 -> 16393 Gain compensation will be enabled with specified value
3937 * 1 -> 16393 Gain compensation is enabled with returned value
4043 * (default setting for compatibility with some ADC on other
4139 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
4154 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
4223 * @note Usage of ADC trigger frequency mode with ADC low power mode:
4413 * - For devices with sequencer fully configurable
4423 * - For devices with sequencer not fully configurable
4480 * - For devices with sequencer fully configurable
4490 * - For devices with sequencer not fully configurable
4705 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
4707 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
4740 * with parts of literals LL_ADC_CHANNEL_x or using
4745 * process the returned value with the helper macro
4816 * comparison with internal channel parameter to be done
4895 * This function can be used with setting "not fully configurable".
4961 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_REG_SetSequencerChannels()
4979 * This function can be used with setting "not fully configurable".
5045 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_REG_SetSequencerChAdd()
5063 * This function can be used with setting "not fully configurable".
5129 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_REG_SetSequencerChRem()
5145 * This function can be used with setting "not fully configurable".
5341 * (with startup time between trigger and start of sampling).
5342 * This feature can be combined with low power mode "auto wait".
5364 * (with startup time between trigger and start of sampling).
5365 * This feature can be combined with low power mode "auto wait".
5532 * This ADC mode is intended to be used with DMA mode non-circular.
5536 * This ADC mode is intended to be used with DMA mode circular.
5570 * This ADC mode is intended to be used with DMA mode non-circular.
5574 * This ADC mode is intended to be used with DMA mode circular.
5598 * @note Compatibility with devices without feature overrun:
5602 * Therefore, for compatibility with all devices, parameter
5648 * (default setting for compatibility with some ADC on other
5656 * ADC must not be disabled. Can be enabled with or without conversion
5735 /* to match with triggers literals definition. */ in LL_ADC_INJ_GetTriggerSource()
5763 * ADC must not be disabled. Can be enabled with or without conversion
5803 * ADC must not be disabled. Can be enabled with or without conversion
5886 * ADC must not be disabled. Can be enabled with or without conversion
5935 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_INJ_SetSequencerRanks()
5937 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_INJ_SetSequencerRanks()
5954 * with parts of literals LL_ADC_CHANNEL_x or using
5959 * process the returned value with the helper macro
6005 * comparison with internal channel parameter to be done
6021 * updated after one ADC conversion trigger and with data
6029 * ADC group injected automatic trigger is compliant only with
6090 * ADC must not be disabled. Can be enabled with or without conversion
6274 /* Set bits with content of parameter "Rankx_Channel" with bits position */ in LL_ADC_INJ_ConfigQueueContext()
6276 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ in LL_ADC_INJ_ConfigQueueContext()
6412 /* Set bits with content of parameter "SamplingTime" with bits position */ in LL_ADC_SetChannelSamplingTime()
6414 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
6427 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
6672 * with analog watchdog from sequencer channel definition,
6794 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ in LL_ADC_SetAnalogWDMonitChannels()
6796 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ in LL_ADC_SetAnalogWDMonitChannels()
6833 * with parts of literals LL_ADC_CHANNEL_x or using
6838 * process the returned value with the helper macro
7086 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_SetAnalogWDThresholds()
7089 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_SetAnalogWDThresholds()
7128 * threshold low or raw data with ADC thresholds high and low
7255 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ in LL_ADC_ConfigAnalogWDThresholds()
7258 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ in LL_ADC_ConfigAnalogWDThresholds()
7586 * or multimode (for devices with several ADC instances).
7593 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7617 * or multimode (for devices with several ADC instances).
7643 * each ADC uses its own DMA channel, with its individual
7651 * This ADC mode is intended to be used with DMA mode non-circular.
7655 * This ADC mode is intended to be used with DMA mode circular.
7665 * is a raw data with ADC master and slave concatenated.
7691 * each ADC uses its own DMA channel, with its individual
7699 * This ADC mode is intended to be used with DMA mode non-circular.
7703 * This ADC mode is intended to be used with DMA mode circular.
7713 * is a raw data with ADC master and slave concatenated.
7740 * This check can be done with function @ref LL_ADC_IsEnabled() for each
7832 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableDeepPowerDown()
7834 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableDeepPowerDown()
7853 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_DisableDeepPowerDown()
7855 /* to not interfere with bits with HW property "rs". */ in LL_ADC_DisableDeepPowerDown()
7886 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableInternalRegulator()
7888 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableInternalRegulator()
7935 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Enable()
7937 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Enable()
7953 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Disable()
7955 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Disable()
7986 * or differential (for devices with differential mode available).
7993 * @note For devices with differential mode available:
8016 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StartCalibration()
8018 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StartCalibration()
8070 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StartConversion()
8072 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StartConversion()
8080 * ADC must be enabled with conversion on going on group regular,
8088 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StopConversion()
8090 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StopConversion()
8122 * with feature oversampling).
8135 * @note For devices with feature oversampling: Oversampling
8150 * @note For devices with feature oversampling: Oversampling
8165 * @note For devices with feature oversampling: Oversampling
8180 * @note For devices with feature oversampling: Oversampling
8195 * @note For devices with feature oversampling: Oversampling
8210 * or raw data with ADC master and slave concatenated.
8211 * @note If raw data with ADC master and slave concatenated is retrieved,
8263 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StartConversion()
8265 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StartConversion()
8273 * ADC must be enabled with conversion on going on group injected,
8281 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StopConversion()
8283 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StopConversion()
8313 * with feature oversampling).
8337 * @note For devices with feature oversampling: Oversampling
8363 * @note For devices with feature oversampling: Oversampling
8389 * @note For devices with feature oversampling: Oversampling
8415 * @note For devices with feature oversampling: Oversampling
8441 * @note For devices with feature oversampling: Oversampling