Lines Matching +full:requirements +full:- +full:dev
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripherals registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
59 …/****** Cortex-A Processor Specific Interrupt Numbers *******************************************…
83 …NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt …
180 …CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt …
183 …SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt …
235 …WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins …
256 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
263 /* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals =…
264 #define __CORTEX_A 7U /*!< Cortex-A# Core */
302 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address of…
315 …uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C …
320 …uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C …
325 …uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C …
339 …SERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
352 …__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC…
373 …[4]; /*!< Reserved, 0x030 - 0x03C */
382 …[8]; /*!< Reserved, 0x060 - 0x07C */
409 …[2]; /*!< Reserved, 0x0E8 - 0x0EC */
439 …__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x…
469 uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
487 …uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0…
514 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
515 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
516 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
517 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
518 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
519 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
520 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
521 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
522 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
532 …ED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */
546 …ED0[2]; /*!< Reserved Address offset: 0x008-0x00C */
553 …ED2[2]; /*!< Reserved Address offset: 0x028-0x02C */
557 …ED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */
559 …ED4[3]; /*!< Reserved Address offset: 0x054-0x05C */
562 …ED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */
564 …ED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */
572 …ED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */
574 …ED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */
584 …ED9[5]; /*!< Reserved Address offset: 0x124-0x134 */
587 …ED10[16]; /*!< Reserved Address offset: 0x140-0x17C */
601 …ED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */
605 …ED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */
612 …ED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */
616 …ED17[4]; /*!< Reserved Address offset: 0x230-0x23C */
619 …ED18[2]; /*!< Reserved Address offset: 0x248-0x24C */
628 …ED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */
634 …ED23[3]; /*!< Reserved Address offset: 0x314-0x31C */
637 …ED24[17]; /*!< Reserved Address offset: 0x328-0x368 */
640 …ED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */
645 …ED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */
651 …ED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */
654 …ED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */
676 …t32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */
684 …t32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */
720 … uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */
727 … uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */
734 … uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */
741 … uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */
748 … uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */
799 uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */
845 …uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 …
871 __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */
899 …uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 …
916 …uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x…
952 …__IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Addre…
953 …uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B …
973 … /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
983 …uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB …
984 … /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
985 … /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
986 …uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 …
987 … /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
988 …uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 …
990 …uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF …
992 …uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B …
996 …__IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Addre…
997 …uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 …
1009 …uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F …
1011 …uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF …
1018 … /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */
1019 …uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F …
1021 …uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC …
1039 … /*!< Reserved Address offset: 0x0018-0x004C */
1046 … /*!< Reserved Address offset: 0x0068-0x006C */
1048 … /*!< Reserved Address offset: 0x0074-0x008C */
1063 … /*!< Reserved Address offset: 0x00C8-0x00CC */
1067 …__IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Ad…
1068 … /*!< Reserved Address offset: 0x00E0-0x00F4 */
1070 … /*!< Reserved Address offset: 0x00FC-0x010C */
1073 … /*!< Reserved Address offset: 0x0118-0x011C */
1076 … /*!< Reserved Address offset: 0x0128-0x01FC */
1079 … /*!< Reserved Address offset: 0x0208-0x02FC */
1088 …; /*!< Reserved Address offset: 0x0320-0x06FC */
1094 … /*!< Reserved Address offset: 0x0714-0x0748 */
1097 …; /*!< Reserved Address offset: 0x0754-0x0764 */
1099 …0]; /*!< Reserved Address offset: 0x076C-0x0790 */
1102 …0]; /*!< Reserved Address offset: 0x079C-0x07C0 */
1104 …; /*!< Reserved Address offset: 0x07C8-0x07E8 */
1109 …]; /*!< Reserved Address offset: 0x07FC-0x08FC */
1112 … /*!< Reserved Address offset: 0x0908-0x090C */
1117 … /*!< Reserved Address offset: 0x0920-0x092C */
1120 … /*!< Reserved Address offset: 0x0938-0x093C */
1125 …; /*!< Reserved Address offset: 0x0950-0x0ADC */
1127 … /*!< Reserved Address offset: 0x0AE4-0x0AFC */
1129 …__IO uint32_t MACSSIR; /*!< Sub-second increment register Ad…
1137 … /*!< Reserved Address offset: 0x0B24-0x0B2C */
1140 … /*!< Reserved Address offset: 0x0B38-0x0B3C */
1149 … /*!< Reserved Address offset: 0x0B60-0x0B6C */
1151 … /*!< Reserved Address offset: 0x0B74-0x0B7C */
1156 … /*!< Reserved Address offset: 0x0B90-0x0BBC */
1162 … /*!< Reserved Address offset: 0x0BD4-0x0BFC */
1164 … /*!< Reserved Address offset: 0x0C04-0x0C1C */
1166 … /*!< Reserved Address offset: 0x0C24-0x0CFC */
1170 … /*!< Reserved Address offset: 0x0D0C-0x0D10 */
1172 … /*!< Reserved Address offset: 0x0D18-0x0D28 */
1194 …; /*!< Reserved Address offset: 0x0D80-0x0FFC */
1199 … /*!< Reserved Address offset: 0x1010-0x101C */
1203 … /*!< Reserved Address offset: 0x102C-0x10FC */
1207 … /*!< Reserved Address offset: 0x110C-0x1110 */
1228 … /*!< Reserved Address offset: 0x1164-0x1168 */
1230 … /*!< Reserved Address offset: 0x1170-0x117C */
1233 … /*!< Reserved Address offset: 0x1188-0x1190 */
1235 … /*!< Reserved Address offset: 0x1198-0x119C */
1237 … /*!< Reserved Address offset: 0x11A4-0x11A8 */
1245 … /*!< Reserved Address offset: 0x11C8-0x11D0 */
1247 … /*!< Reserved Address offset: 0x11D8-0x11DC */
1249 … /*!< Reserved Address offset: 0x11E4-0x11E8 */
1265 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1272 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 …
1279 …uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C …
1281 …uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C …
1283 … /*!< Reserved, Address offset: 0x84 - 0x8C */
1285 … /*!< Reserved, Address offset: 0x94 - 0x9C */
1287 … /*!< Reserved, Address offset: 0xA4 - 0xBC */
1290 … /*!< Reserved, Address offset: 0xC8 - 0xCC */
1293 … /*!< Reserved, Address offset: 0xD8 - 0xDC */
1296 …uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC …
1320 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 …
1323 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1326 …uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 …
1336 … BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1337 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), …
1346 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1361 uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */
1376 uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */
1394 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: …
1399 … AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */
1403 … RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */
1429 …*!< Reserved, Address offset: 0x08-0x14 */
1436 …*!< Reserved, Address offset: 0x30-0x40 */
1438 …*!< Reserved, Address offset: 0x48-0x54 */
1440 …*!< Reserved, Address offset: 0x5C-0x3F0 */
1458 * @brief Inter-integrated Circuit Interface
1474 uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
1493 uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */
1514 …ved20[4]; /* Reserved Address offset: 20h-2Ch */
1521 …ved48[2]; /* Reserved Address offset: 48h-4Ch */
1522 …MEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1523 …MEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1524 …MEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1525 …MEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1526 …UFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1527 …UFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1528 …UFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1529 …HTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1531 …UFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1532 …UFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1533 …UFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1534 …UFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1550 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
1554 * @brief LCD-TFT Display Controller
1559 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1565 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1579 * @brief LCD-TFT Display layer x Controller
1609 uint32_t RESERVED1[64]; /*!< Reserved Address offset: 0x00C-0x108 */
1611 uint32_t RESERVED2[63]; /*!< Reserved Address offset: 0x110-0x208 */
1613 uint32_t RESERVED3[891]; /*!< Reserved Address offset: 0x210-0xFF8 */
1626 uint8_t RESERVED0[0x100 - 0x10];
1674 uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */
1676 uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */
1678 __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1679 …__IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0…
1680 …__IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0…
1690 uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */
1692 __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1693 __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
1694 __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */
1726 … uint32_t RESERVED0[2]; /*!< Reserved, 0x18-0x1C Address offset: 0x18 */
1731 … uint32_t RESERVED1[241]; /*!< Reserved, 0x30-0x3F0 Address offset: 0x30 */
1745 …uint32_t RESERVED0[2]; /*!< Reserved, 0x04-0x08 Addr…
1752 …__IO uint32_t ASSCKSELR; /*!< RCC AXI Sub-System Clock Selection Register …
1756 …uint32_t RESERVED2[2]; /*!< Reserved, 0x34-0x38 Addr…
1760 …__IO uint32_t MSSCKSELR; /*!< RCC MCU Sub-System Clock Selection Register …
1761 …uint32_t RESERVED3[13]; /*!< Reserved, 0x4C-0x7C Addr…
1772 …uint32_t RESERVED4[6]; /*!< Reserved, 0xA8-0xBC Addr…
1781 …uint32_t RESERVED6[8]; /*!< Reserved, 0xE0-0xFC Addr…
1788 …uint32_t RESERVED7[10]; /*!< Reserved, 0x118-0x13C Addr…
1791 …uint32_t RESERVED8[14]; /*!< Reserved, 0x148-0x17C Addr…
1802 …uint32_t RESERVED9[22]; /*!< Reserved, 0x1A8-0x1FC Addr…
1811 …uint32_t RESERVED10[24]; /*!< Reserved, 0x220-0x27C Add…
1820 …uint32_t RESERVED11[24]; /*!< Reserved, 0x2A0-0x2FC Addr…
1829 …uint32_t RESERVED12[24]; /*!< Reserved, 0x320-0x30C Addr…
1838 …uint32_t RESERVED13[24]; /*!< Reserved, 0x3A0-0x3FC Addr…
1848 …uint32_t RESERVED14[247]; /*!< Reserved, 0x424-0x7FC Addr…
1853 …uint32_t RESERVED15[4]; /*!< Reserved, 0x810-0x81C Addr…
1862 …uint32_t RESERVED16[16]; /*!< Reserved, 0x840-0x87C Addr…
1873 …uint32_t RESERVED17[6]; /*!< Reserved, 0x8A8-0x8BC Addr…
1904 …uint32_t RESERVED20[18]; /*!< Reserved, 0x938-0x97C Addr…
1917 …uint32_t RESERVED21[20]; /*!< Reserved, 0x9B0-0x9FC Addr…
1930 …uint32_t RESERVED22[2]; /*!< Reserved, 0xA30-0xA34 Addr…
1933 …uint32_t RESERVED23[16]; /*!< Reserved, 0x940-0xA7C Addr…
1950 …uint32_t RESERVED24[16]; /*!< Reserved, 0xAC0-0xAFC Addr…
1967 …uint32_t RESERVED25[16]; /*!< Reserved, 0xB40-0xB7C Addr…
1984 …uint32_t RESERVED26[16]; /*!< Reserved, 0xBC0-0xBFC Addr…
1986 …uint32_t RESERVED27[4]; /*!< Reserved, 0xC04-0xC10 Addr…
1989 …uint32_t RESERVED28[246]; /*!< Reserved, 0xC1C-0xFF0 Addr…
2003 …uint32_t RESERVED0[2]; /*!< Reserved, 0x08-0x0C Addr…
2008 …uint32_t RESERVED1[245]; /*!< Reserved, 0x20-0x3F4 Addr…
2067 …uint32_t RESERVED0xB8[82]; /*!< Reserved, 0x0B8-0x200 Addr…
2069 …uint32_t RESERVED0x380[796]; /*!< Reserved, 0x0380-0xFF0 Addr…
2084 * @brief Real-Time Clock
2091 …__IO uint32_t SSR; /*!< RTC sub-second register, Addr…
2136 …uint32_t RESERVED2[2]; /*!< Reserved, 0x024 - 0x028 …
2143 …uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C …
2145 …uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC …
2178 …uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 …
2194 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
2197 uint32_t RESERVED1[233]; /*!< Reserved, 0x4C - 0x3EC */
2232 * @brief SPDIF-RX Interface
2244 uint32_t RESERVED2[246]; /*!< Reserved, 0x1C - 0x3F0 */
2274 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
2282 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
2283 …nt32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
2284 …uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 …
2299 uint32_t Reserved[249]; /* Reserved Address offset: 0x08 - 0x3F0 */
2311 …__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-…
2312 …__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-…
2321 …Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
2324 …served1[169]; /* Reserved Address offset: 148h-3E8h */
2355 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
2357 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
2363 …uint32_t RESERVED3[231]; /*!< Reserved, 0x54-0x3EC …
2389 …uint32_t RESERVED[239]; /*!< Reserved, 0x34-0x3EC …
2433 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
2439 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
2449 …uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3…
2470 …uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC …
2518 uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */
2553 uint32_t RESERVED1[249]; /*!< Reserved, 0x0C - 0x3EC */
2583 …__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address o…
2584 …__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address o…
2585 …__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address o…
2586 …__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address o…
2618 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
2621 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
2622 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
2638 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
2650 …__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC…
2658 * @brief Inter-Processor Communication
2662 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
2663 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
2664 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
2665 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
2666 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
2667 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
2668 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
2669 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
2671 …__IO uint32_t HWCFGR; /*!< Inter-Processor Communication hardware configuration register…
2672 …__IO uint32_t VER; /*!< Inter-Processor Communication version register, …
2673 …__IO uint32_t ID; /*!< Inter-Processor Communication identification register, …
2674 …__IO uint32_t SID; /*!< Inter-Processor Communication size identification register, …
2698 … /*!< Reserved, Address offset: 0x01C - 0x0FC */
2763 uint32_t RESERVED1[124]; /*!< Reserved 0x200 - 0x3EC */
2791 uint32_t Reserved5[4]; /*!< Reserved 040h-048h */
2794 uint32_t Reserved43[42]; /*!< Reserved 058h-0FFh */
2796 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
2805 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
2806 __IO uint32_t DCTL; /*!< dev Control Register 804h */
2807 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
2809 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
2810 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
2811 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
2812 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
2815 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
2816 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
2817 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
2818 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
2823 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2829 * @brief USB_OTG_IN_Endpoint-Specific_Register
2833 …__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
2835 …__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
2840 …uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2845 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2849 …__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 0…
2851 …__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 0…
2853 …__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 1…
2854 …__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 1…
2855 …uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1…
3830 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift…
3833 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift…
3836 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift…
3839 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift…
4858 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
4920 /******************** Bit definition for ADC2_OR - Option Register ********************/
4923 …EN ADC2_OR_VDDCOREEN_Msk /*!< ADC2 Option Register - VDDCORE enable bit */
5263 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
5776 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-match…
5779 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-match…
6621 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
6686 /* HDMI-CEC (CEC) */
6743 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
6749 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
6773 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
6776 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
6784 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
6790 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
6814 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
6817 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
6835 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data registe…
7204 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-…
7207 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-…
7210 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-b…
7213 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-…
7216 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-…
7219 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-b…
7224 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
7227 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-…
7232 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
7235 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-…
7240 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
7243 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-b…
7700 …-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF config…
7711 … /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low freq…
7723 … /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/D…
7729 …TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is…
7742 …ired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LR…
7752 …s mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operatin…
7757 …R_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 mod…
7837 …ks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the…
7840 …WN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programm…
7843 … /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the tr…
7852 … /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */
7857 …mmand channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC comman…
7865 …X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */
7892 …clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of …
7912 …PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; …
7915 …-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a …
7931 …fc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), i…
7940 …EFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto…
8201 …MM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIM…
8204 …N_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-ran…
8268 … DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any oper…
8287 …R DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */
8316 …sed only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */
8375 #define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum t…
8385 …_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh…
8507 …N_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB…
8539 …_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ re…
8542 …DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at…
8545 …S_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL ge…
8588 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
8626 …-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect t…
8636 …he de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of…
8644 …ble signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, mainta…
8682 … DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface hands…
8702 …PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_r…
8728 …TRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */
8731 …hen \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */
8763 …D2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */
8829 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Fu…
8836 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Fu…
8843 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Fu…
8850 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Fu…
8859 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - F…
8866 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - F…
8874 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - F…
8882 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - F…
8892 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< -…
8900 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< -…
9088 …-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer …
9109 …empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */
9233 …G0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled…
9238 …_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transaction…
9290 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
9309 …ONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register t…
9378 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9400 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
9405 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9556 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9578 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
9583 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
10135 #define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */
10378 #define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back…
10384 #define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forw…
10889 #define DDRPHYC_MR0_PD DDRPHYC_MR0_PD_Msk /*!< Power-down control */
10952 #define DDRPHYC_MR2_PASR DDRPHYC_MR2_PASR_Msk /*!< Partial array self-refresh */
10964 #define DDRPHYC_MR2_ASR DDRPHYC_MR2_ASR_Msk /*!< Auto self-refresh */
10967 #define DDRPHYC_MR2_SRT DDRPHYC_MR2_SRT_Msk /*!< Self-refresh temperature range */
10992 #define DDRPHYC_MR3_MPRLOC DDRPHYC_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) l…
10997 #define DDRPHYC_MR3_MPR DDRPHYC_MR3_MPR_Msk /*!< Multi-purpose register enable …
11336 #define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */
11339 #define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver…
11342 #define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */
11411 #define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11417 #define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11423 #define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11429 #define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11563 #define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */
11566 #define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver…
11569 #define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */
11638 #define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11644 #define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11650 #define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11656 #define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11790 #define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */
11793 #define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver…
11796 #define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */
11865 #define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11871 #define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11877 #define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11883 #define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
12017 #define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */
12020 #define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver…
12023 #define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */
12092 #define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
12098 #define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
12104 #define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
12110 #define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
12283 …FFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offse…
12286 … DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
12536 …_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting co…
12587 …L ETH_MACCR_BL_Msk /*!< Back-Off Limit */
12603 … /*!< Enable Carrier Sense Before Transmission in Full-Duplex Mode */
12642 … ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */
12693 … ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable */
12696 … ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */
12744 … ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packe…
12871 … ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag Comparis…
12877 …_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */
12880 … ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */
12961 …VL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
12996 …SVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
13019 … ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */
13436 …ER ETH_MACVR_USERVER_Msk /*!< ST-defined version */
13483 … ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Ena…
13956 …CR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /*!< Full-Half Preset */
14938 …TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
14941 …TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
14969 … ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment …
14980 … ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Valu…
15030 … ETH_MACSTNR_TSSS_Msk /*!< Timestamp Sub-seconds */
15103 … ETH_MACSTNUR_TSSS_Msk /*!< Timestamp Sub-seconds */
15380 … ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingres…
15417 … ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress…
16035 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
16041 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
16100 … ETH_MTLRXQ0DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
16412 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
16418 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
16477 … ETH_MTLRXQ1DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
16561 … ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */
18382 #define DSI_VMCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-Power Vertica…
18383 …VBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-Porch Enabl…
18384 …FPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enabl…
18385 #define DSI_VMCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-Power Vertica…
18386 …BPE ((uint32_t)0x00001000U) /*!< Low-Power Horizontal Back-Porch Enab…
18387 …PE ((uint32_t)0x00002000U) /*!< Low-Power Horizontal Front-Porch Enab…
18388 #define DSI_VMCR_FBTAAE ((uint32_t)0x00004000U) /*!< Frame Bus-Turn-Ar…
18389 #define DSI_VMCR_LPCE ((uint32_t)0x00008000U) /*!< Low-Power Command…
18459 #define DSI_VHBPCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-P…
18505 #define DSI_VVBPCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Por…
18518 #define DSI_VVFPCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Po…
18666 #define DSI_TCCR0_LPRX_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-power Recepti…
18684 #define DSI_TCCR0_HSTX_TOCNT ((uint32_t)0xFFFF0000U) /*!< High-Speed Transm…
18703 #define DSI_TCCR1_HSRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Read T…
18722 #define DSI_TCCR2_LPRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Read Ti…
18741 #define DSI_TCCR3_HSWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Write …
18762 #define DSI_TCCR4_LPWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Write T…
18781 #define DSI_TCCR5_BTA_TOCNT ((uint32_t)0x0000FFFFU) /*!< Bus-Turn-Around T…
18813 #define DSI_CLCR_DPCC ((uint32_t)0x00000001U) /*!< D-PHY Clock Contr…
18817 …TCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
18829 …TCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
18842 …TCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
18854 …TCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
18932 #define DSI_ISR1_TOHSTX ((uint32_t)0x00000001U) /*!< Timeout High-Spee…
18933 #define DSI_ISR1_TOLPRX ((uint32_t)0x00000002U) /*!< Timeout Low-Power…
18934 #define DSI_ISR1_ECCSE ((uint32_t)0x00000004U) /*!< ECC Single-bit Er…
18935 #define DSI_ISR1_ECCME ((uint32_t)0x00000008U) /*!< ECC Multi-bit Err…
18970 #define DSI_IER1_TOHSTXIE ((uint32_t)0x00000001U) /*!< Timeout High-Spee…
18971 #define DSI_IER1_TOLPRXIE ((uint32_t)0x00000002U) /*!< Timeout Low-Power…
18972 #define DSI_IER1_ECCSEIE ((uint32_t)0x00000004U) /*!< ECC Single-bit Er…
18973 #define DSI_IER1_ECCMEIE ((uint32_t)0x00000008U) /*!< ECC Multi-bit Err…
19008 …X ((uint32_t)0x00000001U) /*!< Force Timeout High-Speed Transmission */
19009 …OLPRX ((uint32_t)0x00000002U) /*!< Force Timeout Low-Power Reception */
19010 #define DSI_FIR1_FECCSE ((uint32_t)0x00000004U) /*!< Force ECC Single-…
19011 #define DSI_FIR1_FECCME ((uint32_t)0x00000008U) /*!< Force ECC Multi-b…
19084 #define DSI_VMCCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-power Vertica…
19085 …PVBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-porch Enabl…
19086 …VFPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enabl…
19087 #define DSI_VMCCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-power Vertica…
19088 …HBPE ((uint32_t)0x00001000U) /*!< Low-power Horizontal Back-porch Enab…
19089 …FE ((uint32_t)0x00002000U) /*!< Low-power Horizontal Front-porch Enab…
19091 #define DSI_VMCCR_LPCE ((uint32_t)0x00008000U) /*!< Low-power Command…
19158 #define DSI_VHBPCCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-P…
19204 #define DSI_VVBPCCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Por…
19217 #define DSI_VVFPCCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Po…
19314 #define DSI_WPCR0_HSICL ((uint32_t)0x00000200U) /*!< Invert the high-s…
19315 #define DSI_WPCR0_HSIDL0 ((uint32_t)0x00000400U) /*!< Invert the high-s…
19316 #define DSI_WPCR0_HSIDL1 ((uint32_t)0x00000800U) /*!< Invert the high-s…
19331 #define DSI_WPCR1_LPTXSRCL ((uint32_t)0x000000C0U) /*!< Low-Power TX Slew…
19335 #define DSI_WPCR1_LPTXSRDL ((uint32_t)0x00000300U) /*!< Low-Power TX Slew…
19341 …_HSTXSRUCL ((uint32_t)0x00010000U) /*!< High-Speed TX Slew-Rate Up Clock …
19342 …_HSTXSRDCL ((uint32_t)0x00020000U) /*!< High-Speed TX Slew-Rate Down Cloc…
19343 …_HSTXSRUDL ((uint32_t)0x00040000U) /*!< High-Speed TX Slew-Rate Up Data L…
19344 …_HSTXSRDDL ((uint32_t)0x00080000U) /*!< High-Speed TX Slew-Rate Down Data…
21188 … FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21196 … FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21253 … FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21261 … FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21318 … FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21326 … FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21383 … FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21391 … FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21469 … FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21477 … FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21535 … FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21543 … FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21592 … FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21600 … FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21649 … FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21657 … FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
22941 …_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register re…
23740 /* Inter-integrated Circuit Interface (I2C) */
23817 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
23820 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
23849 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
24011 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
24016 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
24132 /* LCD-TFT Display Controller (LTDC) */
24176 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT control…
24415 /* Inter-Processor Communication Controller (IPCC) */
25103 … MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
25412 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
25424 … PWR_CR1_LVDS_Msk /*!< Low Voltage Deepsleep LP-STOP mode selection */
25514 #define PWR_CR3_DDRSREN PWR_CR3_DDRSREN_Msk /*!< DDR self-refres…
25517 #define PWR_CR3_DDRSRDIS PWR_CR3_DDRSRDIS_Msk /*!< DDR self-refres…
25731 #define BSEC_OTP_CONFIG_PWRUP BSEC_OTP_CONFIG_PWRUP_Msk /*!< OTP power-up co…
25810 #define BSEC_DENABLE_NIDEN BSEC_DENABLE_NIDEN_Msk /*!< non-invasive de…
25822 … BSEC_DENABLE_SPNIDEN_Msk /*!< secure privilege non-invasive debug enable…
25825 …BSEC_DENABLE_CP15SDISABLE_Msk /*!< write access to some secure Cortex®-A7 CP15 registers dis…
26113 … RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */
26119 … RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch s…
26140 … RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider …
26151 … RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider …
26194 … RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch s…
26595 …_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command…
26902 … RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
26922 … RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
27135 … RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
27152 … RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
27346 … RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27349 … RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
27369 … RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27372 … RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
27591 … RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27594 … RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
27611 … RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27614 … RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
28076 … RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock outp…
28109 … RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready fl…
28613 … RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock sou…
28742 … RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */
28822 … RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */
29198 … RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
29278 … RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
29676 … RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
29759 … RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
30167 …N RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
30247 …N RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
30667 …N RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
30750 …N RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
31349 /* Real-Time Clock (RTC) */
32662 /* SPDIF-RX Interface */
32698 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
32756 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
33222 …M SAI_HWCFGR_SPDIF_PDM_Msk /*!< Support of SPDIF-OUT and PDM interface…
33925 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode …
33931 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polyn…
34019 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Dat…
34110 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet availa…
34113 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space …
34128 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet availa…
34583 #define SYSCFG_BOOTR_BOOT0_PD SYSCFG_BOOTR_BOOT0_PD_Msk /*!< BOOT0 pin pull-…
34586 #define SYSCFG_BOOTR_BOOT1_PD SYSCFG_BOOTR_BOOT1_PD_Msk /*!< BOOT1 pin pull-…
34589 #define SYSCFG_BOOTR_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD_Msk /*!< BOOT2 pin pull-…
34824 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!< Cortex-M4 LOCKU…
34986 … ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selectio…
34990 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload prel…
35228 /*----------------------------------------------------------------------------*/
35309 /*----------------------------------------------------------------------------*/
35402 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-relo…
35439 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
35457 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
35460 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
36398 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
36407 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
36432 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
36452 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
36496 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
36499 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
36504 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
36518 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
36521 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
36560 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
36621 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate …
36686 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
36689 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
36927 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
36943 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
37086 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral se…
37089 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral se…
37092 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral se…
37095 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral se…
37119 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid…
37122 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid…
37136 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only…
37147 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length …
37198 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeou…
37237 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on progra…
37307 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
37310 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
37313 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
37324 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power c…
37330 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resum…
37469 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SE…
37849 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up dete…
38133 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed devic…
38414 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SE…
38543 …RFRED USBPHYC_TUNE1_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
38579 …HSFALLPREEM USBPHYC_TUNE1_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
38614 …RFRED USBPHYC_TUNE2_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
38650 …HSFALLPREEM USBPHYC_TUNE2_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
38942 /******************** TIM Instances : Advanced-control timers *****************/
39310 /********************* UART Instances : Half-Duplex mode **********************/
39340 /****************** UART Instances : Wake-up from Stop mode *******************/
39398 #define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39401 #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
39404 #define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39407 #define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39410 #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
39414 #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39417 #define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
39420 #define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39423 #define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
39426 #define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
39429 #define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39432 #define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
39435 #define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
39438 #define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
39441 #define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
39444 #define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
39447 #define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39450 #define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39453 #define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39456 #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39459 #define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39462 #define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR)
39465 #define CRYP_VERSION(INSTANCE) ((INSTANCE)->VERR)
39468 #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39471 #define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39474 #define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39477 #define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39480 #define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39483 #define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39486 #define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39489 #define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39492 #define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
39495 #define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
39498 #define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
39501 #define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
39504 #define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39507 #define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39510 #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
39513 #define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39516 #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39519 #define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39522 #define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_…
39526 #define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
39533 #define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYS…