Lines Matching +full:requirements +full:- +full:dev
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripherals registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
59 …/****** Cortex-M Processor Exceptions Numbers ***************************************************…
60 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
61 …HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt …
62 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
63 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
64 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
65 …SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt …
66 …DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt …
67 …PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt …
68 …SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt …
164 …CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt …
167 …SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt …
198 …nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 …
199 …nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 …
219 …WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins …
234 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
236 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
242 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
268 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address of…
281 …uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C …
286 …uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C …
291 …uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C …
305 …SERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
318 …__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC…
339 …[4]; /*!< Reserved, 0x030 - 0x03C */
348 …[8]; /*!< Reserved, 0x060 - 0x07C */
375 …[2]; /*!< Reserved, 0x0E8 - 0x0EC */
405 …__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x…
435 uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
453 …uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0…
480 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
481 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
482 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
483 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
484 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
485 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
486 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
487 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
488 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
498 …ED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */
512 …ED0[2]; /*!< Reserved Address offset: 0x008-0x00C */
519 …ED2[2]; /*!< Reserved Address offset: 0x028-0x02C */
523 …ED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */
525 …ED4[3]; /*!< Reserved Address offset: 0x054-0x05C */
528 …ED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */
530 …ED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */
538 …ED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */
540 …ED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */
550 …ED9[5]; /*!< Reserved Address offset: 0x124-0x134 */
553 …ED10[16]; /*!< Reserved Address offset: 0x140-0x17C */
567 …ED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */
571 …ED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */
578 …ED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */
582 …ED17[4]; /*!< Reserved Address offset: 0x230-0x23C */
585 …ED18[2]; /*!< Reserved Address offset: 0x248-0x24C */
594 …ED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */
600 …ED23[3]; /*!< Reserved Address offset: 0x314-0x31C */
603 …ED24[17]; /*!< Reserved Address offset: 0x328-0x368 */
606 …ED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */
611 …ED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */
617 …ED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */
620 …ED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */
642 …t32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */
650 …t32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */
686 … uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */
693 … uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */
700 … uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */
707 … uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */
714 … uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */
765 uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */
811 …uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 …
837 __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */
865 …uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 …
882 …uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x…
918 …__IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Addre…
919 …uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B …
939 … /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
949 …uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB …
950 … /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
951 … /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
952 …uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 …
953 … /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
954 …uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 …
956 …uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF …
958 …uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B …
962 …__IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Addre…
963 …uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 …
975 …uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F …
977 …uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF …
984 … /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */
985 …uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F …
987 …uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC …
1005 … /*!< Reserved Address offset: 0x0018-0x004C */
1012 … /*!< Reserved Address offset: 0x0068-0x006C */
1014 … /*!< Reserved Address offset: 0x0074-0x008C */
1029 … /*!< Reserved Address offset: 0x00C8-0x00CC */
1033 …__IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Ad…
1034 … /*!< Reserved Address offset: 0x00E0-0x00F4 */
1036 … /*!< Reserved Address offset: 0x00FC-0x010C */
1039 … /*!< Reserved Address offset: 0x0118-0x011C */
1042 … /*!< Reserved Address offset: 0x0128-0x01FC */
1045 … /*!< Reserved Address offset: 0x0208-0x02FC */
1054 …; /*!< Reserved Address offset: 0x0320-0x06FC */
1060 … /*!< Reserved Address offset: 0x0714-0x0748 */
1063 …; /*!< Reserved Address offset: 0x0754-0x0764 */
1065 …0]; /*!< Reserved Address offset: 0x076C-0x0790 */
1068 …0]; /*!< Reserved Address offset: 0x079C-0x07C0 */
1070 …; /*!< Reserved Address offset: 0x07C8-0x07E8 */
1075 …]; /*!< Reserved Address offset: 0x07FC-0x08FC */
1078 … /*!< Reserved Address offset: 0x0908-0x090C */
1083 … /*!< Reserved Address offset: 0x0920-0x092C */
1086 … /*!< Reserved Address offset: 0x0938-0x093C */
1091 …; /*!< Reserved Address offset: 0x0950-0x0ADC */
1093 … /*!< Reserved Address offset: 0x0AE4-0x0AFC */
1095 …__IO uint32_t MACSSIR; /*!< Sub-second increment register Ad…
1103 … /*!< Reserved Address offset: 0x0B24-0x0B2C */
1106 … /*!< Reserved Address offset: 0x0B38-0x0B3C */
1115 … /*!< Reserved Address offset: 0x0B60-0x0B6C */
1117 … /*!< Reserved Address offset: 0x0B74-0x0B7C */
1122 … /*!< Reserved Address offset: 0x0B90-0x0BBC */
1128 … /*!< Reserved Address offset: 0x0BD4-0x0BFC */
1130 … /*!< Reserved Address offset: 0x0C04-0x0C1C */
1132 … /*!< Reserved Address offset: 0x0C24-0x0CFC */
1136 … /*!< Reserved Address offset: 0x0D0C-0x0D10 */
1138 … /*!< Reserved Address offset: 0x0D18-0x0D28 */
1160 …; /*!< Reserved Address offset: 0x0D80-0x0FFC */
1165 … /*!< Reserved Address offset: 0x1010-0x101C */
1169 … /*!< Reserved Address offset: 0x102C-0x10FC */
1173 … /*!< Reserved Address offset: 0x110C-0x1110 */
1194 … /*!< Reserved Address offset: 0x1164-0x1168 */
1196 … /*!< Reserved Address offset: 0x1170-0x117C */
1199 … /*!< Reserved Address offset: 0x1188-0x1190 */
1201 … /*!< Reserved Address offset: 0x1198-0x119C */
1203 … /*!< Reserved Address offset: 0x11A4-0x11A8 */
1211 … /*!< Reserved Address offset: 0x11C8-0x11D0 */
1213 … /*!< Reserved Address offset: 0x11D8-0x11DC */
1215 … /*!< Reserved Address offset: 0x11E4-0x11E8 */
1231 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1238 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 …
1245 …uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C …
1247 …uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C …
1249 … /*!< Reserved, Address offset: 0x84 - 0x8C */
1251 … /*!< Reserved, Address offset: 0x94 - 0x9C */
1253 … /*!< Reserved, Address offset: 0xA4 - 0xBC */
1256 … /*!< Reserved, Address offset: 0xC8 - 0xCC */
1259 … /*!< Reserved, Address offset: 0xD8 - 0xDC */
1262 …uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC …
1286 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 …
1289 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1292 …uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 …
1302 … BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1303 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), …
1312 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1327 uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */
1342 uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */
1360 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: …
1365 … AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */
1369 … RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */
1395 …*!< Reserved, Address offset: 0x08-0x14 */
1402 …*!< Reserved, Address offset: 0x30-0x40 */
1404 …*!< Reserved, Address offset: 0x48-0x54 */
1406 …*!< Reserved, Address offset: 0x5C-0x3F0 */
1424 * @brief Inter-integrated Circuit Interface
1440 uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
1459 uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */
1480 …ved20[4]; /* Reserved Address offset: 20h-2Ch */
1487 …ved48[2]; /* Reserved Address offset: 48h-4Ch */
1488 …MEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1489 …MEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1490 …MEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1491 …MEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1492 …UFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1493 …UFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1494 …UFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1495 …HTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1497 …UFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1498 …UFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1499 …UFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1500 …UFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1516 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
1520 * @brief LCD-TFT Display Controller
1525 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1531 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1545 * @brief LCD-TFT Display layer x Controller
1575 uint32_t RESERVED1[64]; /*!< Reserved Address offset: 0x00C-0x108 */
1577 uint32_t RESERVED2[63]; /*!< Reserved Address offset: 0x110-0x208 */
1579 uint32_t RESERVED3[891]; /*!< Reserved Address offset: 0x210-0xFF8 */
1592 uint8_t RESERVED0[0x100 - 0x10];
1640 uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */
1642 uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */
1644 __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1645 …__IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0…
1646 …__IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0…
1656 uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */
1658 __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1659 __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
1660 __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */
1692 … uint32_t RESERVED0[2]; /*!< Reserved, 0x18-0x1C Address offset: 0x18 */
1697 … uint32_t RESERVED1[241]; /*!< Reserved, 0x30-0x3F0 Address offset: 0x30 */
1711 …uint32_t RESERVED0[2]; /*!< Reserved, 0x04-0x08 Addr…
1718 …__IO uint32_t ASSCKSELR; /*!< RCC AXI Sub-System Clock Selection Register …
1722 …uint32_t RESERVED2[2]; /*!< Reserved, 0x34-0x38 Addr…
1726 …__IO uint32_t MSSCKSELR; /*!< RCC MCU Sub-System Clock Selection Register …
1727 …uint32_t RESERVED3[13]; /*!< Reserved, 0x4C-0x7C Addr…
1738 …uint32_t RESERVED4[6]; /*!< Reserved, 0xA8-0xBC Addr…
1747 …uint32_t RESERVED6[8]; /*!< Reserved, 0xE0-0xFC Addr…
1754 …uint32_t RESERVED7[10]; /*!< Reserved, 0x118-0x13C Addr…
1757 …uint32_t RESERVED8[14]; /*!< Reserved, 0x148-0x17C Addr…
1768 …uint32_t RESERVED9[22]; /*!< Reserved, 0x1A8-0x1FC Addr…
1777 …uint32_t RESERVED10[24]; /*!< Reserved, 0x220-0x27C Add…
1786 …uint32_t RESERVED11[24]; /*!< Reserved, 0x2A0-0x2FC Addr…
1795 …uint32_t RESERVED12[24]; /*!< Reserved, 0x320-0x30C Addr…
1804 …uint32_t RESERVED13[24]; /*!< Reserved, 0x3A0-0x3FC Addr…
1814 …uint32_t RESERVED14[247]; /*!< Reserved, 0x424-0x7FC Addr…
1819 …uint32_t RESERVED15[4]; /*!< Reserved, 0x810-0x81C Addr…
1828 …uint32_t RESERVED16[16]; /*!< Reserved, 0x840-0x87C Addr…
1839 …uint32_t RESERVED17[6]; /*!< Reserved, 0x8A8-0x8BC Addr…
1870 …uint32_t RESERVED20[18]; /*!< Reserved, 0x938-0x97C Addr…
1883 …uint32_t RESERVED21[20]; /*!< Reserved, 0x9B0-0x9FC Addr…
1896 …uint32_t RESERVED22[2]; /*!< Reserved, 0xA30-0xA34 Addr…
1899 …uint32_t RESERVED23[16]; /*!< Reserved, 0x940-0xA7C Addr…
1916 …uint32_t RESERVED24[16]; /*!< Reserved, 0xAC0-0xAFC Addr…
1933 …uint32_t RESERVED25[16]; /*!< Reserved, 0xB40-0xB7C Addr…
1950 …uint32_t RESERVED26[16]; /*!< Reserved, 0xBC0-0xBFC Addr…
1952 …uint32_t RESERVED27[4]; /*!< Reserved, 0xC04-0xC10 Addr…
1955 …uint32_t RESERVED28[246]; /*!< Reserved, 0xC1C-0xFF0 Addr…
1969 …uint32_t RESERVED0[2]; /*!< Reserved, 0x08-0x0C Addr…
1974 …uint32_t RESERVED1[245]; /*!< Reserved, 0x20-0x3F4 Addr…
2033 …uint32_t RESERVED0xB8[82]; /*!< Reserved, 0x0B8-0x200 Addr…
2035 …uint32_t RESERVED0x380[796]; /*!< Reserved, 0x0380-0xFF0 Addr…
2050 * @brief Real-Time Clock
2057 …__IO uint32_t SSR; /*!< RTC sub-second register, Addr…
2102 …uint32_t RESERVED2[2]; /*!< Reserved, 0x024 - 0x028 …
2109 …uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C …
2111 …uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC …
2144 …uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 …
2160 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
2163 uint32_t RESERVED1[233]; /*!< Reserved, 0x4C - 0x3EC */
2198 * @brief SPDIF-RX Interface
2210 uint32_t RESERVED2[246]; /*!< Reserved, 0x1C - 0x3F0 */
2240 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
2248 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
2249 …nt32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
2250 …uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 …
2265 uint32_t Reserved[249]; /* Reserved Address offset: 0x08 - 0x3F0 */
2277 …__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-…
2278 …__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-…
2287 …Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
2290 …served1[169]; /* Reserved Address offset: 148h-3E8h */
2321 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
2323 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
2329 …uint32_t RESERVED3[231]; /*!< Reserved, 0x54-0x3EC …
2355 …uint32_t RESERVED[239]; /*!< Reserved, 0x34-0x3EC …
2399 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
2405 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
2415 …uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3…
2436 …uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC …
2484 uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */
2519 uint32_t RESERVED1[249]; /*!< Reserved, 0x0C - 0x3EC */
2536 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
2539 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
2540 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
2556 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
2568 …__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC…
2576 * @brief Inter-Processor Communication
2580 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
2581 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
2582 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
2583 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
2584 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
2585 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
2586 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
2587 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
2589 …__IO uint32_t HWCFGR; /*!< Inter-Processor Communication hardware configuration register…
2590 …__IO uint32_t VER; /*!< Inter-Processor Communication version register, …
2591 …__IO uint32_t ID; /*!< Inter-Processor Communication identification register, …
2592 …__IO uint32_t SID; /*!< Inter-Processor Communication size identification register, …
2616 … /*!< Reserved, Address offset: 0x01C - 0x0FC */
2681 uint32_t RESERVED1[124]; /*!< Reserved 0x200 - 0x3EC */
2709 uint32_t Reserved5[4]; /*!< Reserved 040h-048h */
2712 uint32_t Reserved43[42]; /*!< Reserved 058h-0FFh */
2714 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
2723 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
2724 __IO uint32_t DCTL; /*!< dev Control Register 804h */
2725 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
2727 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
2728 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
2729 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
2730 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
2733 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
2734 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
2735 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
2736 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
2741 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2747 * @brief USB_OTG_IN_Endpoint-Specific_Register
2751 …__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
2753 …__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
2758 …uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2763 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2767 …__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 0…
2769 …__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 0…
2771 …__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 1…
2772 …__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 1…
2773 …uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1…
3744 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift…
3747 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift…
3750 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift…
3753 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift…
4772 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
4834 /******************** Bit definition for ADC2_OR - Option Register ********************/
4837 …EN ADC2_OR_VDDCOREEN_Msk /*!< ADC2 Option Register - VDDCORE enable bit */
5177 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
5690 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-match…
5693 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-match…
6535 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
6600 /* HDMI-CEC (CEC) */
6657 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
6663 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
6687 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
6690 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
6698 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
6704 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
6728 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
6731 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
6749 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data registe…
6973 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-…
6976 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-…
6979 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-b…
6982 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-…
6985 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-…
6988 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-b…
6993 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
6996 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-…
7001 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
7004 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-…
7009 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
7012 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-b…
7469 …-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF config…
7480 … /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low freq…
7492 … /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/D…
7498 …TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is…
7511 …ired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LR…
7521 …s mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operatin…
7526 …R_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 mod…
7606 …ks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the…
7609 …WN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programm…
7612 … /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the tr…
7621 … /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */
7626 …mmand channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC comman…
7634 …X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */
7661 …clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of …
7681 …PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; …
7684 …-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a …
7700 …fc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), i…
7709 …EFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto…
7970 …MM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIM…
7973 …N_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-ran…
8037 … DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any oper…
8056 …R DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */
8085 …sed only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */
8144 #define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum t…
8154 …_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh…
8276 …N_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB…
8308 …_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ re…
8311 …DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at…
8314 …S_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL ge…
8357 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
8395 …-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect t…
8405 …he de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of…
8413 …ble signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, mainta…
8451 … DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface hands…
8471 …PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_r…
8497 …TRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */
8500 …hen \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */
8532 …D2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */
8598 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Fu…
8605 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Fu…
8612 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Fu…
8619 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Fu…
8628 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - F…
8635 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - F…
8643 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - F…
8651 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - F…
8661 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< -…
8669 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< -…
8857 …-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer …
8878 …empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */
9002 …G0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled…
9007 …_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transaction…
9059 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
9078 …ONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register t…
9147 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9169 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
9174 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9325 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9347 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
9352 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9904 #define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */
10147 #define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back…
10153 #define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forw…
10658 #define DDRPHYC_MR0_PD DDRPHYC_MR0_PD_Msk /*!< Power-down control */
10721 #define DDRPHYC_MR2_PASR DDRPHYC_MR2_PASR_Msk /*!< Partial array self-refresh */
10733 #define DDRPHYC_MR2_ASR DDRPHYC_MR2_ASR_Msk /*!< Auto self-refresh */
10736 #define DDRPHYC_MR2_SRT DDRPHYC_MR2_SRT_Msk /*!< Self-refresh temperature range */
10761 #define DDRPHYC_MR3_MPRLOC DDRPHYC_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) l…
10766 #define DDRPHYC_MR3_MPR DDRPHYC_MR3_MPR_Msk /*!< Multi-purpose register enable …
11105 #define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */
11108 #define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver…
11111 #define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */
11180 #define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11186 #define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11192 #define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11198 #define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11332 #define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */
11335 #define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver…
11338 #define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */
11407 #define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11413 #define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11419 #define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11425 #define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11559 #define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */
11562 #define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver…
11565 #define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */
11634 #define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11640 #define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11646 #define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11652 #define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11786 #define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */
11789 #define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver…
11792 #define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */
11861 #define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11867 #define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11873 #define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11879 #define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
12052 …FFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offse…
12055 … DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
12305 …_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting co…
12356 …L ETH_MACCR_BL_Msk /*!< Back-Off Limit */
12372 … /*!< Enable Carrier Sense Before Transmission in Full-Duplex Mode */
12411 … ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */
12462 … ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable */
12465 … ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */
12513 … ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packe…
12640 … ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag Comparis…
12646 …_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */
12649 … ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */
12730 …VL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
12765 …SVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
12788 … ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */
13205 …ER ETH_MACVR_USERVER_Msk /*!< ST-defined version */
13252 … ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Ena…
13725 …CR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /*!< Full-Half Preset */
14707 …TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
14710 …TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
14738 … ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment …
14749 … ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Valu…
14799 … ETH_MACSTNR_TSSS_Msk /*!< Timestamp Sub-seconds */
14872 … ETH_MACSTNUR_TSSS_Msk /*!< Timestamp Sub-seconds */
15149 … ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingres…
15186 … ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress…
15804 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
15810 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
15869 … ETH_MTLRXQ0DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
16181 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
16187 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
16246 … ETH_MTLRXQ1DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
16330 … ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */
18151 #define DSI_VMCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-Power Vertica…
18152 …VBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-Porch Enabl…
18153 …FPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enabl…
18154 #define DSI_VMCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-Power Vertica…
18155 …BPE ((uint32_t)0x00001000U) /*!< Low-Power Horizontal Back-Porch Enab…
18156 …PE ((uint32_t)0x00002000U) /*!< Low-Power Horizontal Front-Porch Enab…
18157 #define DSI_VMCR_FBTAAE ((uint32_t)0x00004000U) /*!< Frame Bus-Turn-Ar…
18158 #define DSI_VMCR_LPCE ((uint32_t)0x00008000U) /*!< Low-Power Command…
18228 #define DSI_VHBPCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-P…
18274 #define DSI_VVBPCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Por…
18287 #define DSI_VVFPCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Po…
18435 #define DSI_TCCR0_LPRX_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-power Recepti…
18453 #define DSI_TCCR0_HSTX_TOCNT ((uint32_t)0xFFFF0000U) /*!< High-Speed Transm…
18472 #define DSI_TCCR1_HSRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Read T…
18491 #define DSI_TCCR2_LPRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Read Ti…
18510 #define DSI_TCCR3_HSWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Write …
18531 #define DSI_TCCR4_LPWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Write T…
18550 #define DSI_TCCR5_BTA_TOCNT ((uint32_t)0x0000FFFFU) /*!< Bus-Turn-Around T…
18582 #define DSI_CLCR_DPCC ((uint32_t)0x00000001U) /*!< D-PHY Clock Contr…
18586 …TCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
18598 …TCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
18611 …TCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
18623 …TCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
18701 #define DSI_ISR1_TOHSTX ((uint32_t)0x00000001U) /*!< Timeout High-Spee…
18702 #define DSI_ISR1_TOLPRX ((uint32_t)0x00000002U) /*!< Timeout Low-Power…
18703 #define DSI_ISR1_ECCSE ((uint32_t)0x00000004U) /*!< ECC Single-bit Er…
18704 #define DSI_ISR1_ECCME ((uint32_t)0x00000008U) /*!< ECC Multi-bit Err…
18739 #define DSI_IER1_TOHSTXIE ((uint32_t)0x00000001U) /*!< Timeout High-Spee…
18740 #define DSI_IER1_TOLPRXIE ((uint32_t)0x00000002U) /*!< Timeout Low-Power…
18741 #define DSI_IER1_ECCSEIE ((uint32_t)0x00000004U) /*!< ECC Single-bit Er…
18742 #define DSI_IER1_ECCMEIE ((uint32_t)0x00000008U) /*!< ECC Multi-bit Err…
18777 …X ((uint32_t)0x00000001U) /*!< Force Timeout High-Speed Transmission */
18778 …OLPRX ((uint32_t)0x00000002U) /*!< Force Timeout Low-Power Reception */
18779 #define DSI_FIR1_FECCSE ((uint32_t)0x00000004U) /*!< Force ECC Single-…
18780 #define DSI_FIR1_FECCME ((uint32_t)0x00000008U) /*!< Force ECC Multi-b…
18853 #define DSI_VMCCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-power Vertica…
18854 …PVBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-porch Enabl…
18855 …VFPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enabl…
18856 #define DSI_VMCCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-power Vertica…
18857 …HBPE ((uint32_t)0x00001000U) /*!< Low-power Horizontal Back-porch Enab…
18858 …FE ((uint32_t)0x00002000U) /*!< Low-power Horizontal Front-porch Enab…
18860 #define DSI_VMCCR_LPCE ((uint32_t)0x00008000U) /*!< Low-power Command…
18927 #define DSI_VHBPCCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-P…
18973 #define DSI_VVBPCCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Por…
18986 #define DSI_VVFPCCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Po…
19083 #define DSI_WPCR0_HSICL ((uint32_t)0x00000200U) /*!< Invert the high-s…
19084 #define DSI_WPCR0_HSIDL0 ((uint32_t)0x00000400U) /*!< Invert the high-s…
19085 #define DSI_WPCR0_HSIDL1 ((uint32_t)0x00000800U) /*!< Invert the high-s…
19100 #define DSI_WPCR1_LPTXSRCL ((uint32_t)0x000000C0U) /*!< Low-Power TX Slew…
19104 #define DSI_WPCR1_LPTXSRDL ((uint32_t)0x00000300U) /*!< Low-Power TX Slew…
19110 …_HSTXSRUCL ((uint32_t)0x00010000U) /*!< High-Speed TX Slew-Rate Up Clock …
19111 …_HSTXSRDCL ((uint32_t)0x00020000U) /*!< High-Speed TX Slew-Rate Down Cloc…
19112 …_HSTXSRUDL ((uint32_t)0x00040000U) /*!< High-Speed TX Slew-Rate Up Data L…
19113 …_HSTXSRDDL ((uint32_t)0x00080000U) /*!< High-Speed TX Slew-Rate Down Data…
20957 … FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
20965 … FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21022 … FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21030 … FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21087 … FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21095 … FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21152 … FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21160 … FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21238 … FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21246 … FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21304 … FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21312 … FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21361 … FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21369 … FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21418 … FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
21426 … FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
22710 …_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register re…
23509 /* Inter-integrated Circuit Interface (I2C) */
23586 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
23589 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
23618 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
23780 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
23785 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
23901 /* LCD-TFT Display Controller (LTDC) */
23945 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT control…
24184 /* Inter-Processor Communication Controller (IPCC) */
24872 … MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
25181 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
25193 … PWR_CR1_LVDS_Msk /*!< Low Voltage Deepsleep LP-STOP mode selection */
25283 #define PWR_CR3_DDRSREN PWR_CR3_DDRSREN_Msk /*!< DDR self-refres…
25286 #define PWR_CR3_DDRSRDIS PWR_CR3_DDRSRDIS_Msk /*!< DDR self-refres…
25500 #define BSEC_OTP_CONFIG_PWRUP BSEC_OTP_CONFIG_PWRUP_Msk /*!< OTP power-up co…
25579 #define BSEC_DENABLE_NIDEN BSEC_DENABLE_NIDEN_Msk /*!< non-invasive de…
25591 … BSEC_DENABLE_SPNIDEN_Msk /*!< secure privilege non-invasive debug enable…
25594 …BSEC_DENABLE_CP15SDISABLE_Msk /*!< write access to some secure Cortex®-A7 CP15 registers dis…
25882 … RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */
25888 … RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch s…
25909 … RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider …
25920 … RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider …
25963 … RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch s…
26364 …_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command…
26671 … RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
26691 … RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
26904 … RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
26921 … RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
27115 … RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27118 … RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
27138 … RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27141 … RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
27360 … RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27363 … RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
27380 … RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
27383 … RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
27845 … RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock outp…
27878 … RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready fl…
28382 … RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock sou…
28511 … RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */
28591 … RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */
28967 … RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
29047 … RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
29445 … RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
29528 … RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
29936 …N RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
30016 …N RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
30436 …N RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
30519 …N RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
31118 /* Real-Time Clock (RTC) */
32431 /* SPDIF-RX Interface */
32467 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
32525 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
32991 …M SAI_HWCFGR_SPDIF_PDM_Msk /*!< Support of SPDIF-OUT and PDM interface…
33694 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode …
33700 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polyn…
33788 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Dat…
33879 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet availa…
33882 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space …
33897 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet availa…
34352 #define SYSCFG_BOOTR_BOOT0_PD SYSCFG_BOOTR_BOOT0_PD_Msk /*!< BOOT0 pin pull-…
34355 #define SYSCFG_BOOTR_BOOT1_PD SYSCFG_BOOTR_BOOT1_PD_Msk /*!< BOOT1 pin pull-…
34358 #define SYSCFG_BOOTR_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD_Msk /*!< BOOT2 pin pull-…
34593 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!< Cortex-M4 LOCKU…
34755 … ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selectio…
34759 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload prel…
34997 /*----------------------------------------------------------------------------*/
35078 /*----------------------------------------------------------------------------*/
35171 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-relo…
35208 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
35226 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
35229 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
36167 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
36176 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
36201 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
36221 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
36265 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
36268 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
36273 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
36287 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
36290 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
36329 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
36390 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate …
36455 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
36458 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
36696 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
36712 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
36855 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral se…
36858 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral se…
36861 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral se…
36864 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral se…
36888 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid…
36891 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid…
36905 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only…
36916 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length …
36967 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeou…
37006 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on progra…
37076 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
37079 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
37082 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
37093 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power c…
37099 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resum…
37238 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SE…
37618 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up dete…
37902 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed devic…
38183 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SE…
38312 …RFRED USBPHYC_TUNE1_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
38348 …HSFALLPREEM USBPHYC_TUNE1_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
38383 …RFRED USBPHYC_TUNE2_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
38419 …HSFALLPREEM USBPHYC_TUNE2_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
38711 /******************** TIM Instances : Advanced-control timers *****************/
39079 /********************* UART Instances : Half-Duplex mode **********************/
39109 /****************** UART Instances : Wake-up from Stop mode *******************/
39167 #define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39170 #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
39173 #define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39176 #define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39179 #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
39183 #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39186 #define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
39189 #define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39192 #define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
39195 #define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
39198 #define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39201 #define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
39204 #define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
39207 #define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
39210 #define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
39213 #define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
39216 #define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39219 #define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39222 #define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39225 #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39228 #define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39231 #define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR)
39235 #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39238 #define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39241 #define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39244 #define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39247 #define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39250 #define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
39253 #define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
39256 #define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39259 #define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
39262 #define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
39265 #define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
39268 #define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
39271 #define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39274 #define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39277 #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
39280 #define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39283 #define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR)
39286 #define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
39289 #define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_…
39293 #define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
39300 #define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYS…