Lines Matching +full:requirements +full:- +full:dev
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripherals registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
59 …/****** Cortex-A Processor Specific Interrupt Numbers *******************************************…
83 …NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt …
180 …CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt …
183 …SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt …
235 …WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins …
256 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
263 /* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals =…
264 #define __CORTEX_A 7U /*!< Cortex-A# Core */
302 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address of…
315 …uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C …
320 …uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C …
325 …uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C …
339 …SERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
352 …__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC…
373 …[4]; /*!< Reserved, 0x030 - 0x03C */
382 …[8]; /*!< Reserved, 0x060 - 0x07C */
409 …[2]; /*!< Reserved, 0x0E8 - 0x0EC */
439 …__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x…
469 uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
487 …uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0…
514 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
515 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
516 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
517 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
518 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
519 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
520 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
521 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
522 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
532 …ED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */
546 …ED0[2]; /*!< Reserved Address offset: 0x008-0x00C */
553 …ED2[2]; /*!< Reserved Address offset: 0x028-0x02C */
557 …ED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */
559 …ED4[3]; /*!< Reserved Address offset: 0x054-0x05C */
562 …ED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */
564 …ED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */
572 …ED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */
574 …ED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */
584 …ED9[5]; /*!< Reserved Address offset: 0x124-0x134 */
587 …ED10[16]; /*!< Reserved Address offset: 0x140-0x17C */
601 …ED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */
605 …ED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */
612 …ED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */
616 …ED17[4]; /*!< Reserved Address offset: 0x230-0x23C */
619 …ED18[2]; /*!< Reserved Address offset: 0x248-0x24C */
628 …ED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */
634 …ED23[3]; /*!< Reserved Address offset: 0x314-0x31C */
637 …ED24[17]; /*!< Reserved Address offset: 0x328-0x368 */
640 …ED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */
645 …ED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */
651 …ED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */
654 …ED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */
676 …t32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */
684 …t32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */
720 … uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */
727 … uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */
734 … uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */
741 … uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */
748 … uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */
799 uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */
845 …uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 …
871 __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */
899 …uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 …
916 …uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x…
952 … /*!< Reserved Address offset: 0x0018-0x004C */
959 … /*!< Reserved Address offset: 0x0068-0x006C */
961 … /*!< Reserved Address offset: 0x0074-0x008C */
976 … /*!< Reserved Address offset: 0x00C8-0x00CC */
980 …__IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Ad…
981 … /*!< Reserved Address offset: 0x00E0-0x00F4 */
983 … /*!< Reserved Address offset: 0x00FC-0x010C */
986 … /*!< Reserved Address offset: 0x0118-0x011C */
989 … /*!< Reserved Address offset: 0x0128-0x01FC */
992 … /*!< Reserved Address offset: 0x0208-0x02FC */
1001 …; /*!< Reserved Address offset: 0x0320-0x06FC */
1007 … /*!< Reserved Address offset: 0x0714-0x0748 */
1010 …; /*!< Reserved Address offset: 0x0754-0x0764 */
1012 …0]; /*!< Reserved Address offset: 0x076C-0x0790 */
1015 …0]; /*!< Reserved Address offset: 0x079C-0x07C0 */
1017 …; /*!< Reserved Address offset: 0x07C8-0x07E8 */
1022 …]; /*!< Reserved Address offset: 0x07FC-0x08FC */
1025 … /*!< Reserved Address offset: 0x0908-0x090C */
1030 … /*!< Reserved Address offset: 0x0920-0x092C */
1033 … /*!< Reserved Address offset: 0x0938-0x093C */
1038 …; /*!< Reserved Address offset: 0x0950-0x0ADC */
1040 … /*!< Reserved Address offset: 0x0AE4-0x0AFC */
1042 …__IO uint32_t MACSSIR; /*!< Sub-second increment register Ad…
1050 … /*!< Reserved Address offset: 0x0B24-0x0B2C */
1053 … /*!< Reserved Address offset: 0x0B38-0x0B3C */
1062 … /*!< Reserved Address offset: 0x0B60-0x0B6C */
1064 … /*!< Reserved Address offset: 0x0B74-0x0B7C */
1069 … /*!< Reserved Address offset: 0x0B90-0x0BBC */
1075 … /*!< Reserved Address offset: 0x0BD4-0x0BFC */
1077 … /*!< Reserved Address offset: 0x0C04-0x0C1C */
1079 … /*!< Reserved Address offset: 0x0C24-0x0CFC */
1083 … /*!< Reserved Address offset: 0x0D0C-0x0D10 */
1085 … /*!< Reserved Address offset: 0x0D18-0x0D28 */
1107 …; /*!< Reserved Address offset: 0x0D80-0x0FFC */
1112 … /*!< Reserved Address offset: 0x1010-0x101C */
1116 … /*!< Reserved Address offset: 0x102C-0x10FC */
1120 … /*!< Reserved Address offset: 0x110C-0x1110 */
1141 … /*!< Reserved Address offset: 0x1164-0x1168 */
1143 … /*!< Reserved Address offset: 0x1170-0x117C */
1146 … /*!< Reserved Address offset: 0x1188-0x1190 */
1148 … /*!< Reserved Address offset: 0x1198-0x119C */
1150 … /*!< Reserved Address offset: 0x11A4-0x11A8 */
1158 … /*!< Reserved Address offset: 0x11C8-0x11D0 */
1160 … /*!< Reserved Address offset: 0x11D8-0x11DC */
1162 … /*!< Reserved Address offset: 0x11E4-0x11E8 */
1178 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1185 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 …
1192 …uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C …
1194 …uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C …
1196 … /*!< Reserved, Address offset: 0x84 - 0x8C */
1198 … /*!< Reserved, Address offset: 0x94 - 0x9C */
1200 … /*!< Reserved, Address offset: 0xA4 - 0xBC */
1203 … /*!< Reserved, Address offset: 0xC8 - 0xCC */
1206 … /*!< Reserved, Address offset: 0xD8 - 0xDC */
1209 …uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC …
1233 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 …
1236 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1239 …uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 …
1249 … BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1250 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), …
1259 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1274 uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */
1289 uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */
1307 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: …
1312 … AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */
1316 … RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */
1342 …*!< Reserved, Address offset: 0x08-0x14 */
1349 …*!< Reserved, Address offset: 0x30-0x40 */
1351 …*!< Reserved, Address offset: 0x48-0x54 */
1353 …*!< Reserved, Address offset: 0x5C-0x3F0 */
1371 * @brief Inter-integrated Circuit Interface
1387 uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
1406 uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */
1427 …ved20[4]; /* Reserved Address offset: 20h-2Ch */
1434 …ved48[2]; /* Reserved Address offset: 48h-4Ch */
1435 …MEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1436 …MEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1437 …MEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1438 …MEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1439 …UFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1440 …UFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1441 …UFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1442 …HTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1444 …UFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1445 …UFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1446 …UFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1447 …UFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1463 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
1467 * @brief LCD-TFT Display Controller
1472 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1478 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1492 * @brief LCD-TFT Display layer x Controller
1522 uint32_t RESERVED1[64]; /*!< Reserved Address offset: 0x00C-0x108 */
1524 uint32_t RESERVED2[63]; /*!< Reserved Address offset: 0x110-0x208 */
1526 uint32_t RESERVED3[891]; /*!< Reserved Address offset: 0x210-0xFF8 */
1539 uint8_t RESERVED0[0x100 - 0x10];
1587 uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */
1589 uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */
1591 __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1592 …__IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0…
1593 …__IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0…
1603 uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */
1605 __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1606 __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
1607 __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */
1639 … uint32_t RESERVED0[2]; /*!< Reserved, 0x18-0x1C Address offset: 0x18 */
1644 … uint32_t RESERVED1[241]; /*!< Reserved, 0x30-0x3F0 Address offset: 0x30 */
1658 …uint32_t RESERVED0[2]; /*!< Reserved, 0x04-0x08 Addr…
1665 …__IO uint32_t ASSCKSELR; /*!< RCC AXI Sub-System Clock Selection Register …
1669 …uint32_t RESERVED2[2]; /*!< Reserved, 0x34-0x38 Addr…
1673 …__IO uint32_t MSSCKSELR; /*!< RCC MCU Sub-System Clock Selection Register …
1674 …uint32_t RESERVED3[13]; /*!< Reserved, 0x4C-0x7C Addr…
1685 …uint32_t RESERVED4[6]; /*!< Reserved, 0xA8-0xBC Addr…
1694 …uint32_t RESERVED6[8]; /*!< Reserved, 0xE0-0xFC Addr…
1701 …uint32_t RESERVED7[10]; /*!< Reserved, 0x118-0x13C Addr…
1704 …uint32_t RESERVED8[14]; /*!< Reserved, 0x148-0x17C Addr…
1715 …uint32_t RESERVED9[22]; /*!< Reserved, 0x1A8-0x1FC Addr…
1724 …uint32_t RESERVED10[24]; /*!< Reserved, 0x220-0x27C Add…
1733 …uint32_t RESERVED11[24]; /*!< Reserved, 0x2A0-0x2FC Addr…
1742 …uint32_t RESERVED12[24]; /*!< Reserved, 0x320-0x30C Addr…
1751 …uint32_t RESERVED13[24]; /*!< Reserved, 0x3A0-0x3FC Addr…
1761 …uint32_t RESERVED14[247]; /*!< Reserved, 0x424-0x7FC Addr…
1766 …uint32_t RESERVED15[4]; /*!< Reserved, 0x810-0x81C Addr…
1775 …uint32_t RESERVED16[16]; /*!< Reserved, 0x840-0x87C Addr…
1786 …uint32_t RESERVED17[6]; /*!< Reserved, 0x8A8-0x8BC Addr…
1817 …uint32_t RESERVED20[18]; /*!< Reserved, 0x938-0x97C Addr…
1830 …uint32_t RESERVED21[20]; /*!< Reserved, 0x9B0-0x9FC Addr…
1843 …uint32_t RESERVED22[2]; /*!< Reserved, 0xA30-0xA34 Addr…
1846 …uint32_t RESERVED23[16]; /*!< Reserved, 0x940-0xA7C Addr…
1863 …uint32_t RESERVED24[16]; /*!< Reserved, 0xAC0-0xAFC Addr…
1880 …uint32_t RESERVED25[16]; /*!< Reserved, 0xB40-0xB7C Addr…
1897 …uint32_t RESERVED26[16]; /*!< Reserved, 0xBC0-0xBFC Addr…
1899 …uint32_t RESERVED27[4]; /*!< Reserved, 0xC04-0xC10 Addr…
1902 …uint32_t RESERVED28[246]; /*!< Reserved, 0xC1C-0xFF0 Addr…
1916 …uint32_t RESERVED0[2]; /*!< Reserved, 0x08-0x0C Addr…
1921 …uint32_t RESERVED1[245]; /*!< Reserved, 0x20-0x3F4 Addr…
1980 …uint32_t RESERVED0xB8[82]; /*!< Reserved, 0x0B8-0x200 Addr…
1982 …uint32_t RESERVED0x380[796]; /*!< Reserved, 0x0380-0xFF0 Addr…
1997 * @brief Real-Time Clock
2004 …__IO uint32_t SSR; /*!< RTC sub-second register, Addr…
2049 …uint32_t RESERVED2[2]; /*!< Reserved, 0x024 - 0x028 …
2056 …uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C …
2058 …uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC …
2091 …uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 …
2107 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
2110 uint32_t RESERVED1[233]; /*!< Reserved, 0x4C - 0x3EC */
2145 * @brief SPDIF-RX Interface
2157 uint32_t RESERVED2[246]; /*!< Reserved, 0x1C - 0x3F0 */
2187 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
2195 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
2196 …nt32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
2197 …uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 …
2212 uint32_t Reserved[249]; /* Reserved Address offset: 0x08 - 0x3F0 */
2224 …__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-…
2225 …__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-…
2234 …Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
2237 …served1[169]; /* Reserved Address offset: 148h-3E8h */
2268 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
2270 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
2276 …uint32_t RESERVED3[231]; /*!< Reserved, 0x54-0x3EC …
2302 …uint32_t RESERVED[239]; /*!< Reserved, 0x34-0x3EC …
2346 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
2352 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
2362 …uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3…
2383 …uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC …
2431 uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */
2466 uint32_t RESERVED1[249]; /*!< Reserved, 0x0C - 0x3EC */
2483 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
2486 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
2487 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
2503 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
2515 …__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC…
2523 * @brief Inter-Processor Communication
2527 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
2528 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
2529 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
2530 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
2531 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
2532 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
2533 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
2534 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
2536 …__IO uint32_t HWCFGR; /*!< Inter-Processor Communication hardware configuration register…
2537 …__IO uint32_t VER; /*!< Inter-Processor Communication version register, …
2538 …__IO uint32_t ID; /*!< Inter-Processor Communication identification register, …
2539 …__IO uint32_t SID; /*!< Inter-Processor Communication size identification register, …
2563 … /*!< Reserved, Address offset: 0x01C - 0x0FC */
2628 uint32_t RESERVED1[124]; /*!< Reserved 0x200 - 0x3EC */
2656 uint32_t Reserved5[4]; /*!< Reserved 040h-048h */
2659 uint32_t Reserved43[42]; /*!< Reserved 058h-0FFh */
2661 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
2670 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
2671 __IO uint32_t DCTL; /*!< dev Control Register 804h */
2672 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
2674 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
2675 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
2676 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
2677 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
2680 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
2681 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
2682 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
2683 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
2688 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2694 * @brief USB_OTG_IN_Endpoint-Specific_Register
2698 …__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
2700 …__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
2705 …uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2710 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2714 …__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 0…
2716 …__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 0…
2718 …__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 1…
2719 …__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 1…
2720 …uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1…
3663 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift…
3666 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift…
3669 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift…
3672 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift…
4691 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
4753 /******************** Bit definition for ADC2_OR - Option Register ********************/
4756 …EN ADC2_OR_VDDCOREEN_Msk /*!< ADC2 Option Register - VDDCORE enable bit */
5096 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
5609 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-match…
5612 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-match…
6454 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
6519 /* HDMI-CEC (CEC) */
6576 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
6582 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
6606 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
6609 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
6617 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
6623 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
6647 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
6650 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
6668 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data registe…
6892 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-…
6895 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-…
6898 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-b…
6901 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-…
6904 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-…
6907 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-b…
6912 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
6915 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-…
6920 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
6923 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-…
6928 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
6931 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-b…
7388 …-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF config…
7399 … /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low freq…
7411 … /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/D…
7417 …TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is…
7430 …ired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LR…
7440 …s mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operatin…
7445 …R_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 mod…
7525 …ks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the…
7528 …WN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programm…
7531 … /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the tr…
7540 … /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */
7545 …mmand channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC comman…
7553 …X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */
7580 …clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of …
7600 …PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; …
7603 …-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a …
7619 …fc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), i…
7628 …EFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto…
7889 …MM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIM…
7892 …N_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-ran…
7956 … DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any oper…
7975 …R DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */
8004 …sed only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */
8063 #define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum t…
8073 …_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh…
8195 …N_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB…
8227 …_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ re…
8230 …DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at…
8233 …S_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL ge…
8276 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
8314 …-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect t…
8324 …he de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of…
8332 …ble signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, mainta…
8370 … DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface hands…
8390 …PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_r…
8416 …TRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */
8419 …hen \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */
8451 …D2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */
8517 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Fu…
8524 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Fu…
8531 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Fu…
8538 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Fu…
8547 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - F…
8554 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - F…
8562 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - F…
8570 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - F…
8580 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< -…
8588 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< -…
8776 …-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer …
8797 …empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */
8921 …G0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled…
8926 …_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transaction…
8978 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
8997 …ONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register t…
9066 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9088 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
9093 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9244 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9266 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
9271 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
9823 #define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */
10066 #define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back…
10072 #define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forw…
10577 #define DDRPHYC_MR0_PD DDRPHYC_MR0_PD_Msk /*!< Power-down control */
10640 #define DDRPHYC_MR2_PASR DDRPHYC_MR2_PASR_Msk /*!< Partial array self-refresh */
10652 #define DDRPHYC_MR2_ASR DDRPHYC_MR2_ASR_Msk /*!< Auto self-refresh */
10655 #define DDRPHYC_MR2_SRT DDRPHYC_MR2_SRT_Msk /*!< Self-refresh temperature range */
10680 #define DDRPHYC_MR3_MPRLOC DDRPHYC_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) l…
10685 #define DDRPHYC_MR3_MPR DDRPHYC_MR3_MPR_Msk /*!< Multi-purpose register enable …
11024 #define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */
11027 #define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver…
11030 #define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */
11099 #define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11105 #define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11111 #define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11117 #define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11251 #define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */
11254 #define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver…
11257 #define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */
11326 #define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11332 #define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11338 #define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11344 #define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11478 #define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */
11481 #define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver…
11484 #define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */
11553 #define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11559 #define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11565 #define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11571 #define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11705 #define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */
11708 #define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver…
11711 #define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */
11780 #define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
11786 #define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
11792 #define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
11798 #define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
11971 …FFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offse…
11974 … DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
12224 …_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting co…
12275 …L ETH_MACCR_BL_Msk /*!< Back-Off Limit */
12291 … /*!< Enable Carrier Sense Before Transmission in Full-Duplex Mode */
12330 … ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */
12381 … ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable */
12384 … ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */
12432 … ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packe…
12559 … ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag Comparis…
12565 …_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */
12568 … ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */
12649 …VL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
12684 …SVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
12707 … ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */
13124 …ER ETH_MACVR_USERVER_Msk /*!< ST-defined version */
13171 … ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Ena…
13644 …CR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /*!< Full-Half Preset */
14626 …TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
14629 …TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
14657 … ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment …
14668 … ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Valu…
14718 … ETH_MACSTNR_TSSS_Msk /*!< Timestamp Sub-seconds */
14791 … ETH_MACSTNUR_TSSS_Msk /*!< Timestamp Sub-seconds */
15068 … ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingres…
15105 … ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress…
15723 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
15729 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
15788 … ETH_MTLRXQ0DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
16100 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
16106 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
16165 … ETH_MTLRXQ1DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
16249 … ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */
19768 … FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
19776 … FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
19833 … FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
19841 … FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
19898 … FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
19906 … FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
19963 … FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
19971 … FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
20049 … FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
20057 … FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
20115 … FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
20123 … FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
20172 … FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
20180 … FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
20229 … FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
20237 … FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
21521 …_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register re…
22320 /* Inter-integrated Circuit Interface (I2C) */
22397 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
22400 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
22429 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
22591 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
22596 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
22712 /* LCD-TFT Display Controller (LTDC) */
22756 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT control…
22995 /* Inter-Processor Communication Controller (IPCC) */
23683 … MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
23992 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
24004 … PWR_CR1_LVDS_Msk /*!< Low Voltage Deepsleep LP-STOP mode selection */
24094 #define PWR_CR3_DDRSREN PWR_CR3_DDRSREN_Msk /*!< DDR self-refres…
24097 #define PWR_CR3_DDRSRDIS PWR_CR3_DDRSRDIS_Msk /*!< DDR self-refres…
24311 #define BSEC_OTP_CONFIG_PWRUP BSEC_OTP_CONFIG_PWRUP_Msk /*!< OTP power-up co…
24390 #define BSEC_DENABLE_NIDEN BSEC_DENABLE_NIDEN_Msk /*!< non-invasive de…
24402 … BSEC_DENABLE_SPNIDEN_Msk /*!< secure privilege non-invasive debug enable…
24405 …BSEC_DENABLE_CP15SDISABLE_Msk /*!< write access to some secure Cortex®-A7 CP15 registers dis…
24693 … RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */
24699 … RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch s…
24720 … RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider …
24731 … RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider …
24774 … RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch s…
25175 …_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command…
25482 … RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
25502 … RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
25715 … RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
25732 … RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
25926 … RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
25929 … RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
25949 … RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
25952 … RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
26171 … RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
26174 … RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
26191 … RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
26194 … RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
26656 … RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock outp…
26689 … RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready fl…
27193 … RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock sou…
27322 … RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */
27402 … RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */
27778 … RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
27858 … RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
28256 … RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
28339 … RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
28747 …N RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
28827 …N RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
29247 …N RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
29330 …N RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
29929 /* Real-Time Clock (RTC) */
31242 /* SPDIF-RX Interface */
31278 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
31336 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
31802 …M SAI_HWCFGR_SPDIF_PDM_Msk /*!< Support of SPDIF-OUT and PDM interface…
32505 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode …
32511 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polyn…
32599 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Dat…
32690 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet availa…
32693 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space …
32708 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet availa…
33163 #define SYSCFG_BOOTR_BOOT0_PD SYSCFG_BOOTR_BOOT0_PD_Msk /*!< BOOT0 pin pull-…
33166 #define SYSCFG_BOOTR_BOOT1_PD SYSCFG_BOOTR_BOOT1_PD_Msk /*!< BOOT1 pin pull-…
33169 #define SYSCFG_BOOTR_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD_Msk /*!< BOOT2 pin pull-…
33404 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!< Cortex-M4 LOCKU…
33566 … ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selectio…
33570 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload prel…
33808 /*----------------------------------------------------------------------------*/
33889 /*----------------------------------------------------------------------------*/
33982 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-relo…
34019 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
34037 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
34040 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
34978 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
34987 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
35012 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
35032 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
35076 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
35079 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
35084 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
35098 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
35101 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
35140 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
35201 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate …
35266 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
35269 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
35507 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
35523 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
35666 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral se…
35669 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral se…
35672 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral se…
35675 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral se…
35699 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid…
35702 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid…
35716 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only…
35727 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length …
35778 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeou…
35817 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on progra…
35887 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
35890 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
35893 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
35904 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power c…
35910 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resum…
36049 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SE…
36429 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up dete…
36713 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed devic…
36994 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SE…
37123 …RFRED USBPHYC_TUNE1_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
37159 …HSFALLPREEM USBPHYC_TUNE1_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
37194 …RFRED USBPHYC_TUNE2_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
37230 …HSFALLPREEM USBPHYC_TUNE2_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
37522 /******************** TIM Instances : Advanced-control timers *****************/
37890 /********************* UART Instances : Half-Duplex mode **********************/
37920 /****************** UART Instances : Wake-up from Stop mode *******************/
37978 #define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
37981 #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
37984 #define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
37987 #define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
37990 #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
37994 #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
37997 #define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
38000 #define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38003 #define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
38006 #define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
38009 #define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
38012 #define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
38015 #define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
38018 #define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
38021 #define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
38024 #define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
38027 #define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38030 #define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38033 #define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
38036 #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38039 #define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR)
38042 #define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR)
38046 #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
38049 #define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38052 #define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
38055 #define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
38058 #define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
38061 #define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
38064 #define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
38067 #define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
38070 #define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
38073 #define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
38076 #define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
38079 #define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
38082 #define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
38085 #define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38088 #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
38091 #define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38095 #define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
38098 #define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_…
38102 #define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
38109 #define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYS…