Lines Matching +full:requirements +full:- +full:dev
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripherals registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
59 …/****** Cortex-A Processor Specific Interrupt Numbers *******************************************…
83 …NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt …
180 …CEC_IRQn = 126, /*!< HDMI-CEC global Interrupt …
183 …SPDIF_RX_IRQn = 129, /*!< SPDIF-RX global Interrupt …
235 …WAKEUP_PIN_IRQn = 181, /*!< Interrupt for all 6 wake-up pins …
256 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
263 /* =========================== Configuration of the ARM Cortex-A Processor and Core Peripherals =…
264 #define __CORTEX_A 7U /*!< Cortex-A# Core */
302 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address of…
315 …uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C …
320 …uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C …
325 …uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C …
339 …SERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
352 …__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC…
368 uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
386 …uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0…
413 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
414 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
415 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
416 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
417 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
418 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
419 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
420 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
421 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
431 …ED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */
445 …ED0[2]; /*!< Reserved Address offset: 0x008-0x00C */
452 …ED2[2]; /*!< Reserved Address offset: 0x028-0x02C */
456 …ED3[5]; /*!< Reserved Address offset: 0x03C-0x04C */
458 …ED4[3]; /*!< Reserved Address offset: 0x054-0x05C */
461 …ED5[22]; /*!< Reserved Address offset: 0x068-0x0BC */
463 …ED6[2]; /*!< Reserved Address offset: 0x0C4-0x0C8 */
471 …ED7[2]; /*!< Reserved Address offset: 0x0E8-0x0EC */
473 …ED8[3]; /*!< Reserved Address offset: 0x0F4-0x0FC */
483 …ED9[5]; /*!< Reserved Address offset: 0x124-0x134 */
486 …ED10[16]; /*!< Reserved Address offset: 0x140-0x17C */
500 …ED13[2]; /*!< Reserved Address offset: 0x1B4-0x1B8 */
504 …ED15[15]; /*!< Reserved Address offset: 0x1C8-0x200 */
511 …ED16[2]; /*!< Reserved Address offset: 0x21C-0x220 */
515 …ED17[4]; /*!< Reserved Address offset: 0x230-0x23C */
518 …ED18[2]; /*!< Reserved Address offset: 0x248-0x24C */
527 …ED22[36]; /*!< Reserved Address offset: 0x270-0x2FC */
533 …ED23[3]; /*!< Reserved Address offset: 0x314-0x31C */
536 …ED24[17]; /*!< Reserved Address offset: 0x328-0x368 */
539 …ED25[34]; /*!< Reserved Address offset: 0x374-0x3F8 */
544 …ED26[33]; /*!< Reserved Address offset: 0x40C-0x48C */
550 …ED27[4]; /*!< Reserved Address offset: 0x4A4-0x4B0 */
553 …ED28[33]; /*!< Reserved Address offset: 0x4BC-0x53C */
575 …t32_t RESERVED1[3]; /*!< Reserved Address offset: 0x024-0x02C */
583 …t32_t RESERVED5[233]; /*!< Reserved Address offset: 0x04C-0x3EC */
619 … uint32_t RESERVED0[70]; /*!< Reserved Address offset: 0x060-0x174 */
626 … uint32_t RESERVED1[12]; /*!< Reserved Address offset: 0x190-0x1BC */
633 … uint32_t RESERVED2[10]; /*!< Reserved Address offset: 0x1D8-0x1FC */
640 … uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x218-0x23C */
647 … uint32_t RESERVED4[10]; /*!< Reserved Address offset: 0x258-0x27C */
698 uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */
744 …uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 …
770 __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */
798 …uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 …
815 …uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x…
851 … /*!< Reserved Address offset: 0x0018-0x004C */
858 … /*!< Reserved Address offset: 0x0068-0x006C */
860 … /*!< Reserved Address offset: 0x0074-0x008C */
875 … /*!< Reserved Address offset: 0x00C8-0x00CC */
879 …__IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Ad…
880 … /*!< Reserved Address offset: 0x00E0-0x00F4 */
882 … /*!< Reserved Address offset: 0x00FC-0x010C */
885 … /*!< Reserved Address offset: 0x0118-0x011C */
888 … /*!< Reserved Address offset: 0x0128-0x01FC */
891 … /*!< Reserved Address offset: 0x0208-0x02FC */
900 …; /*!< Reserved Address offset: 0x0320-0x06FC */
906 … /*!< Reserved Address offset: 0x0714-0x0748 */
909 …; /*!< Reserved Address offset: 0x0754-0x0764 */
911 …0]; /*!< Reserved Address offset: 0x076C-0x0790 */
914 …0]; /*!< Reserved Address offset: 0x079C-0x07C0 */
916 …; /*!< Reserved Address offset: 0x07C8-0x07E8 */
921 …]; /*!< Reserved Address offset: 0x07FC-0x08FC */
924 … /*!< Reserved Address offset: 0x0908-0x090C */
929 … /*!< Reserved Address offset: 0x0920-0x092C */
932 … /*!< Reserved Address offset: 0x0938-0x093C */
937 …; /*!< Reserved Address offset: 0x0950-0x0ADC */
939 … /*!< Reserved Address offset: 0x0AE4-0x0AFC */
941 …__IO uint32_t MACSSIR; /*!< Sub-second increment register Ad…
949 … /*!< Reserved Address offset: 0x0B24-0x0B2C */
952 … /*!< Reserved Address offset: 0x0B38-0x0B3C */
961 … /*!< Reserved Address offset: 0x0B60-0x0B6C */
963 … /*!< Reserved Address offset: 0x0B74-0x0B7C */
968 … /*!< Reserved Address offset: 0x0B90-0x0BBC */
974 … /*!< Reserved Address offset: 0x0BD4-0x0BFC */
976 … /*!< Reserved Address offset: 0x0C04-0x0C1C */
978 … /*!< Reserved Address offset: 0x0C24-0x0CFC */
982 … /*!< Reserved Address offset: 0x0D0C-0x0D10 */
984 … /*!< Reserved Address offset: 0x0D18-0x0D28 */
1006 …; /*!< Reserved Address offset: 0x0D80-0x0FFC */
1011 … /*!< Reserved Address offset: 0x1010-0x101C */
1015 … /*!< Reserved Address offset: 0x102C-0x10FC */
1019 … /*!< Reserved Address offset: 0x110C-0x1110 */
1040 … /*!< Reserved Address offset: 0x1164-0x1168 */
1042 … /*!< Reserved Address offset: 0x1170-0x117C */
1045 … /*!< Reserved Address offset: 0x1188-0x1190 */
1047 … /*!< Reserved Address offset: 0x1198-0x119C */
1049 … /*!< Reserved Address offset: 0x11A4-0x11A8 */
1057 … /*!< Reserved Address offset: 0x11C8-0x11D0 */
1059 … /*!< Reserved Address offset: 0x11D8-0x11DC */
1061 … /*!< Reserved Address offset: 0x11E4-0x11E8 */
1077 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1084 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 …
1091 …uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C …
1093 …uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C …
1095 … /*!< Reserved, Address offset: 0x84 - 0x8C */
1097 … /*!< Reserved, Address offset: 0x94 - 0x9C */
1099 … /*!< Reserved, Address offset: 0xA4 - 0xBC */
1102 … /*!< Reserved, Address offset: 0xC8 - 0xCC */
1105 … /*!< Reserved, Address offset: 0xD8 - 0xDC */
1108 …uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC …
1132 …uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 …
1135 …uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 …
1138 …uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 …
1148 … BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1149 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), …
1158 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1173 uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */
1188 uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */
1206 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: …
1211 … AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */
1215 … RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */
1241 …*!< Reserved, Address offset: 0x08-0x14 */
1248 …*!< Reserved, Address offset: 0x30-0x40 */
1250 …*!< Reserved, Address offset: 0x48-0x54 */
1252 …*!< Reserved, Address offset: 0x5C-0x3F0 */
1270 * @brief Inter-integrated Circuit Interface
1286 uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
1305 uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */
1326 …ved20[4]; /* Reserved Address offset: 20h-2Ch */
1333 …ved48[2]; /* Reserved Address offset: 48h-4Ch */
1334 …MEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1335 …MEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1336 …MEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1337 …MEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1338 …UFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1339 …UFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1340 …UFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1341 …HTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1343 …UFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1344 …UFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1345 …UFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1346 …UFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1362 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
1366 * @brief LCD-TFT Display Controller
1371 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1377 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1391 * @brief LCD-TFT Display layer x Controller
1421 uint32_t RESERVED1[64]; /*!< Reserved Address offset: 0x00C-0x108 */
1423 uint32_t RESERVED2[63]; /*!< Reserved Address offset: 0x110-0x208 */
1425 uint32_t RESERVED3[891]; /*!< Reserved Address offset: 0x210-0xFF8 */
1438 uint8_t RESERVED0[0x100 - 0x10];
1486 uint32_t RESERVED1[4]; /*!< Reserved, Address offsets: 0x010-0x01C */
1488 uint32_t RESERVED2[1003]; /*!< Reserved, Address offsets: 0x024-0xFCC */
1490 __IO uint32_t RESERVED3[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1491 …__IO uint32_t PIDR[4]; /*!< STGENC Peripheral ID0-ID3 Registers, Address offset: 0…
1492 …__IO uint32_t CIDR[4]; /*!< STGENC Component ID0-ID3 Registers, Address offset: 0…
1502 uint32_t RESERVED1[1010]; /*!< Reserved, Address offsets: 0x008-0xFCC */
1504 __IO uint32_t RESERVED2[3]; /*!< Reserved, Address offsets: 0xFD4-0xFDC */
1505 __IO uint32_t PIDR[4]; /*!< STGENR Peripheral ID0-ID3 Registers, Address offset: 0xFE0 */
1506 __IO uint32_t CIDR[4]; /*!< STGENR Component ID0-ID3 Registers, Address offset: 0xFF0 */
1538 … uint32_t RESERVED0[2]; /*!< Reserved, 0x18-0x1C Address offset: 0x18 */
1543 … uint32_t RESERVED1[241]; /*!< Reserved, 0x30-0x3F0 Address offset: 0x30 */
1557 …uint32_t RESERVED0[2]; /*!< Reserved, 0x04-0x08 Addr…
1564 …__IO uint32_t ASSCKSELR; /*!< RCC AXI Sub-System Clock Selection Register …
1568 …uint32_t RESERVED2[2]; /*!< Reserved, 0x34-0x38 Addr…
1572 …__IO uint32_t MSSCKSELR; /*!< RCC MCU Sub-System Clock Selection Register …
1573 …uint32_t RESERVED3[13]; /*!< Reserved, 0x4C-0x7C Addr…
1584 …uint32_t RESERVED4[6]; /*!< Reserved, 0xA8-0xBC Addr…
1593 …uint32_t RESERVED6[8]; /*!< Reserved, 0xE0-0xFC Addr…
1600 …uint32_t RESERVED7[10]; /*!< Reserved, 0x118-0x13C Addr…
1603 …uint32_t RESERVED8[14]; /*!< Reserved, 0x148-0x17C Addr…
1614 …uint32_t RESERVED9[22]; /*!< Reserved, 0x1A8-0x1FC Addr…
1623 …uint32_t RESERVED10[24]; /*!< Reserved, 0x220-0x27C Add…
1632 …uint32_t RESERVED11[24]; /*!< Reserved, 0x2A0-0x2FC Addr…
1641 …uint32_t RESERVED12[24]; /*!< Reserved, 0x320-0x30C Addr…
1650 …uint32_t RESERVED13[24]; /*!< Reserved, 0x3A0-0x3FC Addr…
1660 …uint32_t RESERVED14[247]; /*!< Reserved, 0x424-0x7FC Addr…
1665 …uint32_t RESERVED15[4]; /*!< Reserved, 0x810-0x81C Addr…
1674 …uint32_t RESERVED16[16]; /*!< Reserved, 0x840-0x87C Addr…
1685 …uint32_t RESERVED17[6]; /*!< Reserved, 0x8A8-0x8BC Addr…
1716 …uint32_t RESERVED20[18]; /*!< Reserved, 0x938-0x97C Addr…
1729 …uint32_t RESERVED21[20]; /*!< Reserved, 0x9B0-0x9FC Addr…
1742 …uint32_t RESERVED22[2]; /*!< Reserved, 0xA30-0xA34 Addr…
1745 …uint32_t RESERVED23[16]; /*!< Reserved, 0x940-0xA7C Addr…
1762 …uint32_t RESERVED24[16]; /*!< Reserved, 0xAC0-0xAFC Addr…
1779 …uint32_t RESERVED25[16]; /*!< Reserved, 0xB40-0xB7C Addr…
1796 …uint32_t RESERVED26[16]; /*!< Reserved, 0xBC0-0xBFC Addr…
1798 …uint32_t RESERVED27[4]; /*!< Reserved, 0xC04-0xC10 Addr…
1801 …uint32_t RESERVED28[246]; /*!< Reserved, 0xC1C-0xFF0 Addr…
1815 …uint32_t RESERVED0[2]; /*!< Reserved, 0x08-0x0C Addr…
1820 …uint32_t RESERVED1[245]; /*!< Reserved, 0x20-0x3F4 Addr…
1879 …uint32_t RESERVED0xB8[82]; /*!< Reserved, 0x0B8-0x200 Addr…
1881 …uint32_t RESERVED0x380[796]; /*!< Reserved, 0x0380-0xFF0 Addr…
1896 * @brief Real-Time Clock
1903 …__IO uint32_t SSR; /*!< RTC sub-second register, Addr…
1948 …uint32_t RESERVED2[2]; /*!< Reserved, 0x024 - 0x028 …
1955 …uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C …
1957 …uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC …
1990 …uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 …
2006 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
2009 uint32_t RESERVED1[233]; /*!< Reserved, 0x4C - 0x3EC */
2044 * @brief SPDIF-RX Interface
2056 uint32_t RESERVED2[246]; /*!< Reserved, 0x1C - 0x3F0 */
2086 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
2094 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
2095 …nt32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
2096 …uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 …
2111 uint32_t Reserved[249]; /* Reserved Address offset: 0x08 - 0x3F0 */
2123 …__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-…
2124 …__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-…
2133 …Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
2136 …served1[169]; /* Reserved Address offset: 148h-3E8h */
2167 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
2169 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
2175 …uint32_t RESERVED3[231]; /*!< Reserved, 0x54-0x3EC …
2201 …uint32_t RESERVED[239]; /*!< Reserved, 0x34-0x3EC …
2245 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
2251 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
2261 …uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3…
2282 …uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC …
2330 uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */
2365 uint32_t RESERVED1[249]; /*!< Reserved, 0x0C - 0x3EC */
2382 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
2385 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
2386 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
2402 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
2414 …__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC…
2422 * @brief Inter-Processor Communication
2426 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
2427 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
2428 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
2429 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
2430 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
2431 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
2432 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
2433 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
2435 …__IO uint32_t HWCFGR; /*!< Inter-Processor Communication hardware configuration register…
2436 …__IO uint32_t VER; /*!< Inter-Processor Communication version register, …
2437 …__IO uint32_t ID; /*!< Inter-Processor Communication identification register, …
2438 …__IO uint32_t SID; /*!< Inter-Processor Communication size identification register, …
2462 … /*!< Reserved, Address offset: 0x01C - 0x0FC */
2527 uint32_t RESERVED1[124]; /*!< Reserved 0x200 - 0x3EC */
2555 uint32_t Reserved5[4]; /*!< Reserved 040h-048h */
2558 uint32_t Reserved43[42]; /*!< Reserved 058h-0FFh */
2560 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
2569 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
2570 __IO uint32_t DCTL; /*!< dev Control Register 804h */
2571 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
2573 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
2574 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
2575 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
2576 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
2579 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
2580 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
2581 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
2582 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
2587 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2593 * @brief USB_OTG_IN_Endpoint-Specific_Register
2597 …__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
2599 …__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
2604 …uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2609 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2613 …__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 0…
2615 …__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 0…
2617 …__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 1…
2618 …__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 1…
2619 …uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1…
3553 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift…
3556 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift…
3559 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift…
3562 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift…
4581 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
4643 /******************** Bit definition for ADC2_OR - Option Register ********************/
4646 …EN ADC2_OR_VDDCOREEN_Msk /*!< ADC2 Option Register - VDDCORE enable bit */
4971 /* HDMI-CEC (CEC) */
5028 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
5034 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
5058 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
5061 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
5069 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
5075 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
5099 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
5102 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
5120 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data registe…
5344 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-…
5347 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-…
5350 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-b…
5353 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-…
5356 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-…
5359 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-b…
5364 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
5367 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-…
5372 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
5375 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-…
5380 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
5383 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-b…
5837 …-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. the burst-chop for Reads is exercised only in HIF config…
5848 … /*!< Set to 1 when the DDRCTRL and DRAM has to be put in DLL-off mode for low freq…
5860 … /*!< Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/D…
5866 …TYPE_Msk /*!< Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is…
5879 …ired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LR…
5889 …s mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operatin…
5894 …R_DATA_Msk /*!< Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 mod…
5974 …ks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the…
5977 …WN_EN_Msk /*!< If true then the DDRCTRL goes into power-down after a programm…
5980 … /*!< When this is 1, DDRCTRL puts the SDRAM into deep power-down mode when the tr…
5989 … /*!< Indicates whether skipping CAM draining is allowed when entering Self-Refresh. */
5994 …mmand channel being idle the DDRCTRL automatically puts the SDRAM into power-down. The DDRC comman…
6002 …X4096 DDRCTRL_PWRTMG_T_DPD_X4096_Msk /*!< Minimum deep power-down time. */
6029 …clock stop, automatic power down or automatic self-refresh modes. Note, it does not cause exit of …
6049 …PER_BANK_REFRESH DDRCTRL_RFSHCTL0_PER_BANK_REFRESH_Msk /*!< - 1 - Per bank refresh; …
6052 …-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a …
6068 …fc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3/LPDDR4 per-bank refresh only), i…
6077 …EFRESH_Msk /*!< When \q1\q, disable auto-refresh generated by the DDRCTRL. When auto…
6338 …MM_STAGGER_CS_EN_Msk /*!< Staggering enable for multi-rank accesses (for multi-rank UDIM…
6341 …N_Msk /*!< Address Mirroring Enable (for multi-rank UDIMM implementations and multi-ran…
6405 … DDRCTRL_DRAMTMG1_T_XP_Msk /*!< tXP: Minimum time after power-down exit to any oper…
6424 …R DDRCTRL_DRAMTMG2_RD2WR_Msk /*!< DDR2/3/mDDR: RL + BL/2 + 2 - WL */
6453 …sed only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. */
6512 #define DDRCTRL_DRAMTMG4_T_RCD DDRCTRL_DRAMTMG4_T_RCD_Msk /*!< tRCD - tAL: Minimum t…
6522 …_Msk /*!< Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh…
6644 …N_DFI_LP_T_STAB DDRCTRL_DRAMTMG15_EN_DFI_LP_T_STAB_Msk /*!< - 1 - Enable using tSTAB…
6676 …_RESISTOR_SHARED DDRCTRL_ZQCTL0_ZQ_RESISTOR_SHARED_Msk /*!< - 1 - Denotes that ZQ re…
6679 …DIS_SRX_ZQCL_Msk /*!< - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at…
6682 …S_AUTO_ZQ DDRCTRL_ZQCTL0_DIS_AUTO_ZQ_Msk /*!< - 1 - Disable DDRCTRL ge…
6725 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
6763 …-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect t…
6773 …he de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of…
6781 …ble signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, mainta…
6819 … DDRCTRL_DFILPCFG0_DFI_LP_EN_DPD_Msk /*!< Enables DFI Low-power interface hands…
6839 …PHY to respond within this time. If the PHY does not respond, the DDRCTRL de-asserts dfi_ctrlupd_r…
6865 …TRL_DFIUPD0_CTRLUPD_PRE_SRX_Msk /*!< Selects dfi_ctrlupd_req requirements at SRX: */
6868 …hen \q1\q, disable the automatic dfi_ctrlupd_req generation by the DDRCTRL at self-refresh exit. */
6900 …D2_DFI_PHYUPD_EN_Msk /*!< Enables the support for acknowledging PHY-initiated updates: */
6966 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B2_Msk /*!< - Fu…
6973 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B3_Msk /*!< - Fu…
6980 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B4_Msk /*!< - Fu…
6987 #define DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5 DDRCTRL_ADDRMAP2_ADDRMAP_COL_B5_Msk /*!< - Fu…
6996 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B6_Msk /*!< - F…
7003 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B7_Msk /*!< - F…
7011 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B8_Msk /*!< - F…
7019 #define DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9 DDRCTRL_ADDRMAP3_ADDRMAP_COL_B9_Msk /*!< - F…
7029 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B10_Msk /*!< -…
7037 #define DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11 DDRCTRL_ADDRMAP4_ADDRMAP_COL_B11_Msk /*!< -…
7225 …-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer …
7246 …empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. */
7370 …G0_DIS_COLLISION_PAGE_OPT_Msk /*!< When this is set to \q0\q, auto-precharge is disabled…
7375 …_DQ DDRCTRL_DBG1_DIS_DQ_Msk /*!< When 1, DDRCTRL does not de-queue any transaction…
7427 … to set this register bit if in Init, in Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or De…
7446 …ONE_Msk /*!< Enable quasi-dynamic register programming outside reset. Program register t…
7515 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
7537 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
7542 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
7693 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
7715 …eful in cases where software coherency is desired for masters issuing back-to-back read/write tran…
7720 …-count every clock cycle where the port is requesting but not granted. The higher significant 5-bi…
8272 #define DDRPHYC_RIDR_UDRID DDRPHYC_RIDR_UDRID_Msk /*!< User-defined rev ID */
8515 #define DDRPHYC_ACDLLCR_MFBDLY DDRPHYC_ACDLLCR_MFBDLY_Msk /*!< Master DLL feed-back…
8521 #define DDRPHYC_ACDLLCR_MFWDLY DDRPHYC_ACDLLCR_MFWDLY_Msk /*!< Master DLL feed-forw…
9026 #define DDRPHYC_MR0_PD DDRPHYC_MR0_PD_Msk /*!< Power-down control */
9089 #define DDRPHYC_MR2_PASR DDRPHYC_MR2_PASR_Msk /*!< Partial array self-refresh */
9101 #define DDRPHYC_MR2_ASR DDRPHYC_MR2_ASR_Msk /*!< Auto self-refresh */
9104 #define DDRPHYC_MR2_SRT DDRPHYC_MR2_SRT_Msk /*!< Self-refresh temperature range */
9129 #define DDRPHYC_MR3_MPRLOC DDRPHYC_MR3_MPRLOC_Msk /*!< Multi-purpose register (MPR) l…
9134 #define DDRPHYC_MR3_MPR DDRPHYC_MR3_MPR_Msk /*!< Multi-purpose register enable …
9473 #define DDRPHYC_DX0GCR_DXPDD DDRPHYC_DX0GCR_DXPDD_Msk /*!< Data power-down driver */
9476 #define DDRPHYC_DX0GCR_DXPDR DDRPHYC_DX0GCR_DXPDR_Msk /*!< Data power-down receiver…
9479 #define DDRPHYC_DX0GCR_DQSRPD DDRPHYC_DX0GCR_DQSRPD_Msk /*!< DQSR power-down */
9548 #define DDRPHYC_DX0DLLCR_SFBDLY DDRPHYC_DX0DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
9554 #define DDRPHYC_DX0DLLCR_SFWDLY DDRPHYC_DX0DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
9560 #define DDRPHYC_DX0DLLCR_MFBDLY DDRPHYC_DX0DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
9566 #define DDRPHYC_DX0DLLCR_MFWDLY DDRPHYC_DX0DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
9700 #define DDRPHYC_DX1GCR_DXPDD DDRPHYC_DX1GCR_DXPDD_Msk /*!< Data power-down driver */
9703 #define DDRPHYC_DX1GCR_DXPDR DDRPHYC_DX1GCR_DXPDR_Msk /*!< Data power-down receiver…
9706 #define DDRPHYC_DX1GCR_DQSRPD DDRPHYC_DX1GCR_DQSRPD_Msk /*!< DQSR power-down */
9775 #define DDRPHYC_DX1DLLCR_SFBDLY DDRPHYC_DX1DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
9781 #define DDRPHYC_DX1DLLCR_SFWDLY DDRPHYC_DX1DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
9787 #define DDRPHYC_DX1DLLCR_MFBDLY DDRPHYC_DX1DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
9793 #define DDRPHYC_DX1DLLCR_MFWDLY DDRPHYC_DX1DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
9927 #define DDRPHYC_DX2GCR_DXPDD DDRPHYC_DX2GCR_DXPDD_Msk /*!< Data power-down driver */
9930 #define DDRPHYC_DX2GCR_DXPDR DDRPHYC_DX2GCR_DXPDR_Msk /*!< Data power-down receiver…
9933 #define DDRPHYC_DX2GCR_DQSRPD DDRPHYC_DX2GCR_DQSRPD_Msk /*!< DQSR power-down */
10002 #define DDRPHYC_DX2DLLCR_SFBDLY DDRPHYC_DX2DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
10008 #define DDRPHYC_DX2DLLCR_SFWDLY DDRPHYC_DX2DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
10014 #define DDRPHYC_DX2DLLCR_MFBDLY DDRPHYC_DX2DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
10020 #define DDRPHYC_DX2DLLCR_MFWDLY DDRPHYC_DX2DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
10154 #define DDRPHYC_DX3GCR_DXPDD DDRPHYC_DX3GCR_DXPDD_Msk /*!< Data power-down driver */
10157 #define DDRPHYC_DX3GCR_DXPDR DDRPHYC_DX3GCR_DXPDR_Msk /*!< Data power-down receiver…
10160 #define DDRPHYC_DX3GCR_DQSRPD DDRPHYC_DX3GCR_DQSRPD_Msk /*!< DQSR power-down */
10229 #define DDRPHYC_DX3DLLCR_SFBDLY DDRPHYC_DX3DLLCR_SFBDLY_Msk /*!< Slave DLL feed-b…
10235 #define DDRPHYC_DX3DLLCR_SFWDLY DDRPHYC_DX3DLLCR_SFWDLY_Msk /*!< Slave DLL feed-f…
10241 #define DDRPHYC_DX3DLLCR_MFBDLY DDRPHYC_DX3DLLCR_MFBDLY_Msk /*!< Master DLL feed-…
10247 #define DDRPHYC_DX3DLLCR_MFWDLY DDRPHYC_DX3DLLCR_MFWDLY_Msk /*!< Master DLL feed-…
10420 …FFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offse…
10423 … DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
10673 …_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting co…
10724 …L ETH_MACCR_BL_Msk /*!< Back-Off Limit */
10740 … /*!< Enable Carrier Sense Before Transmission in Full-Duplex Mode */
10779 … ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */
10830 … ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable */
10833 … ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */
10881 … ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packe…
11008 … ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag Comparis…
11014 …_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */
11017 … ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */
11098 …VL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
11133 …SVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
11156 … ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */
11573 …ER ETH_MACVR_USERVER_Msk /*!< ST-defined version */
11620 … ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Ena…
12093 …CR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /*!< Full-Half Preset */
13075 …TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
13078 …TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
13106 … ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment …
13117 … ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Valu…
13167 … ETH_MACSTNR_TSSS_Msk /*!< Timestamp Sub-seconds */
13240 … ETH_MACSTNUR_TSSS_Msk /*!< Timestamp Sub-seconds */
13517 … ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingres…
13554 … ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress…
14172 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
14178 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
14237 … ETH_MTLRXQ0DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
14549 … /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
14555 … /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
14614 … ETH_MTLRXQ1DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
14698 … ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */
18217 … FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18225 … FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
18282 … FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18290 … FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
18347 … FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18355 … FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
18412 … FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18420 … FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
18498 … FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18506 … FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
18564 … FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18572 … FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
18621 … FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18629 … FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
18678 … FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
18686 … FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
19970 …_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register re…
20769 /* Inter-integrated Circuit Interface (I2C) */
20846 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
20849 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
20878 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
21040 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
21045 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
21161 /* LCD-TFT Display Controller (LTDC) */
21205 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT control…
21444 /* Inter-Processor Communication Controller (IPCC) */
22132 … MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
22441 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
22453 … PWR_CR1_LVDS_Msk /*!< Low Voltage Deepsleep LP-STOP mode selection */
22543 #define PWR_CR3_DDRSREN PWR_CR3_DDRSREN_Msk /*!< DDR self-refres…
22546 #define PWR_CR3_DDRSRDIS PWR_CR3_DDRSRDIS_Msk /*!< DDR self-refres…
22760 #define BSEC_OTP_CONFIG_PWRUP BSEC_OTP_CONFIG_PWRUP_Msk /*!< OTP power-up co…
22839 #define BSEC_DENABLE_NIDEN BSEC_DENABLE_NIDEN_Msk /*!< non-invasive de…
22851 … BSEC_DENABLE_SPNIDEN_Msk /*!< secure privilege non-invasive debug enable…
22854 …BSEC_DENABLE_CP15SDISABLE_Msk /*!< write access to some secure Cortex®-A7 CP15 registers dis…
23142 … RCC_ASSCKSELR_AXISSRC_Msk /*!< AXI sub-system clock switch */
23148 … RCC_ASSCKSELR_AXISSRCRDY_Msk /*!< AXI sub-system clock switch s…
23169 … RCC_MPCKDIVR_MPUDIVRDY_Msk /*!< MPU sub-system clock divider …
23180 … RCC_AXIDIVR_AXIDIVRDY_Msk /*!< AXI sub-system clock divider …
23223 … RCC_MSSCKSELR_MCUSSRCRDY_Msk /*!< MCU sub-system clock switch s…
23624 …_DDRITFCR_DFILP_WIDTH_Msk /*!< Minimum duration of low-power request command…
23931 … RCC_MP_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
23951 … RCC_MP_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
24164 … RCC_MC_APB4ENSETR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
24181 … RCC_MC_APB4ENCLRR_STGENROEN_Msk /*!< STGEN Read-Only interface periph…
24375 … RCC_MP_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
24378 … RCC_MP_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
24398 … RCC_MP_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
24401 … RCC_MP_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
24620 … RCC_MC_APB4LPENSETR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
24623 … RCC_MC_APB4LPENSETR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface, clock…
24640 … RCC_MC_APB4LPENCLRR_STGENROLPEN_Msk /*!< STGEN Read-Only Interface periph…
24643 … RCC_MC_APB4LPENCLRR_STGENROSTPEN_Msk /*!< STGEN Read-Only Interface clock …
25105 … RCC_MCO2CFGR_MCO2SEL_Msk /*!< Micro-controller clock outp…
25138 … RCC_OCRDYR_AXICKRDY_Msk /*!< AXI sub-system clock ready fl…
25642 … RCC_CECCKSELR_CECSRC_Msk /*!< CEC-HDMI kernel clock sou…
25771 … RCC_APB1RSTSETR_CECRST_Msk /*!< HDMI-CEC block reset */
25851 … RCC_APB1RSTCLRR_CECRST_Msk /*!< HDMI-CEC block reset */
26227 … RCC_MP_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
26307 … RCC_MP_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
26705 … RCC_MC_APB1ENSETR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
26788 … RCC_MC_APB1ENCLRR_CECEN_Msk /*!< HDMI-CEC peripheral clocks…
27196 …N RCC_MP_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
27276 …N RCC_MP_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
27696 …N RCC_MC_APB1LPENSETR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
27779 …N RCC_MC_APB1LPENCLRR_CECLPEN_Msk /*!< HDMI-CEC peripheral clocks…
28378 /* Real-Time Clock (RTC) */
29691 /* SPDIF-RX Interface */
29727 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
29785 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
30251 …M SAI_HWCFGR_SPDIF_PDM_Msk /*!< Support of SPDIF-OUT and PDM interface…
30954 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode …
30960 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polyn…
31048 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Dat…
31139 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet availa…
31142 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space …
31157 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet availa…
31612 #define SYSCFG_BOOTR_BOOT0_PD SYSCFG_BOOTR_BOOT0_PD_Msk /*!< BOOT0 pin pull-…
31615 #define SYSCFG_BOOTR_BOOT1_PD SYSCFG_BOOTR_BOOT1_PD_Msk /*!< BOOT1 pin pull-…
31618 #define SYSCFG_BOOTR_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD_Msk /*!< BOOT2 pin pull-…
31853 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!< Cortex-M4 LOCKU…
32015 … ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selectio…
32019 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload prel…
32257 /*----------------------------------------------------------------------------*/
32338 /*----------------------------------------------------------------------------*/
32431 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-relo…
32468 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
32486 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
32489 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
33427 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
33436 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
33461 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
33481 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
33525 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
33528 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
33533 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
33547 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
33550 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
33589 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
33650 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate …
33715 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
33718 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
33956 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
33972 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
34115 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral se…
34118 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral se…
34121 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral se…
34124 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral se…
34148 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid…
34151 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid…
34165 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only…
34176 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length …
34227 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeou…
34266 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on progra…
34336 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
34339 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
34342 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
34353 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power c…
34359 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resum…
34498 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SE…
34878 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up dete…
35162 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed devic…
35443 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SE…
35572 …RFRED USBPHYC_TUNE1_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
35608 …HSFALLPREEM USBPHYC_TUNE1_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
35643 …RFRED USBPHYC_TUNE2_HSDRVRFRED_Msk /*!< High-speed rise-fall reduction e…
35679 …HSFALLPREEM USBPHYC_TUNE2_HSFALLPREEM_Msk /*!< HS fall time pre-emphasis */
35966 /******************** TIM Instances : Advanced-control timers *****************/
36334 /********************* UART Instances : Half-Duplex mode **********************/
36364 /****************** UART Instances : Wake-up from Stop mode *******************/
36422 #define BSEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36425 #define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
36428 #define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36431 #define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
36434 #define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
36438 #define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
36441 #define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
36444 #define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36447 #define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
36450 #define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
36453 #define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
36456 #define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
36459 #define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
36462 #define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
36465 #define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
36468 #define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
36471 #define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36474 #define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36477 #define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
36480 #define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36483 #define RNG_VERSION(INSTANCE) ((INSTANCE)->VERR)
36486 #define HASH_VERSION(INSTANCE) ((INSTANCE)->VERR)
36490 #define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
36493 #define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36496 #define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
36499 #define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
36502 #define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
36505 #define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
36508 #define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
36511 #define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
36514 #define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
36517 #define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
36520 #define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
36523 #define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
36526 #define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
36529 #define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36532 #define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
36535 #define DAC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36539 #define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
36542 #define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_…
36546 #define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
36553 #define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYS…