Lines Matching full:with
14 * If no LICENSE file comes with this software, it is provided AS-IS.
131 …_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other S…
134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
159 …_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other S…
162 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
170 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
358 …RT | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": S…
364 … ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature s…
370 … (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature s…
427 …de configuration to operate in independent mode or multimode (for devices with several ADC instanc…
458 * (setting possible with ADC enabled without conversion on going,
459 * ADC enabled with conversion on going, ...)
460 * Each feature can be updated afterwards with a unitary function
461 * and potentially with ADC in a different state than disabled,
472 … /*!< Configures the left shifting applied to the final result with or without oversamp…
487 * (functions with prefix "REG").
494 * (setting possible with ADC enabled without conversion on going,
495 * ADC enabled with conversion on going, ...)
496 * Each feature can be updated afterwards with a unitary function
497 * and potentially with ADC in a different state than disabled,
506 …(default setting for compatibility with some ADC on other STM32 families having this setting set b…
547 * (functions with prefix "INJ").
554 * (setting possible with ADC enabled without conversion on going,
555 * ADC enabled with conversion on going, ...)
556 * Each feature can be updated afterwards with a unitary function
557 * and potentially with ADC in a different state than disabled,
566 …(default setting for compatibility with some ADC on other STM32 families having this setting set b…
602 * @brief Flags defines which can be used with LL_ADC_ReadReg function
645 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
663 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
666 /* List of ADC registers intended to be used (most commonly) with */
669 …egular conversion data register (corresponding to register DR) to be used with ADC configured in i…
671 … (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 d…
681 … ) /*!< ADC synchronous clock derived from AHB clock with prescaler division …
682 …MODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division …
684 …_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
685 …_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division …
686 …_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
687 …_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division …
688 …_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
689 …_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division …
690 …_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
691 …_PRESC_3) /*!< ADC asynchronous clock with prescaler division …
692 …_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
693 …_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division …
694 …_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
728 …ion of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode a…
729 …Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode a…
730 … calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode a…
787 …en necessary (when previous ADC conversion data is read). See description with function @ref LL_AD…
913 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
914 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
933 … ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequ…
934 … ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequ…
935 … ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequ…
936 …_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequ…
937 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequ…
938 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequ…
939 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequ…
940 … ) /*!< ADC group regular sequencer enable with 9 ranks in the sequ…
941 … | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the seq…
942 … | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the seq…
943 … | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the seq…
944 …_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the seq…
945 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the seq…
946 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the seq…
947 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the seq…
956 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
957 …_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interrupti…
958 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
959 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
960 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
961 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
962 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
963 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1032 …njected conversion trigger from ADC group regular. Setting compliant only with group injected trig…
1051 … ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequ…
1052 … (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequ…
1053 … (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequ…
1062 …_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interrupti…
1259 … /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (…
1270 …ar conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA …
1423 * number is returned, either defined with number
1424 * or with bitfield (only one bit must be set).
1508 * comparison with internal channel parameter to be done
1541 * number in ADC registers. The differentiation is made only with
1660 * number in ADC registers. The differentiation is made only with
1689 * define a single channel to monitor with analog watchdog
1691 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1728 * comparison with internal channel parameter to be done
1835 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1836 * Example, with a ADC resolution of 8 bits, to set the value of
1858 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1859 * Example, with a ADC resolution of 8 bits, to get the value of
1878 * @brief Helper macro to set the ADC calibration value with both single ended
1880 * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
1896 * or ADC slave from raw value with both ADC conversion data concatenated.
1899 * In this case the transferred data need to processed with this macro
1916 * @note In case of device with multimode available and a mix of
1917 * ADC instances compliant and not compliant with multimode feature,
1918 * ADC instances not compliant with multimode feature are
1938 * - Multimode (for devices with several ADC instances)
1949 * @note This check is required by functions with setting conditioned to
1953 * @note On devices with only 1 ADC common instance, parameter of this macro
1955 * with devices featuring several ADC common instances).
2044 * On devices with small package, the pin Vref+ is not present
2079 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2138 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2145 * of the current device has characteristics in line with
2213 * intended to be used (most commonly) with DMA transfer.
2217 * @note This macro is intended to be used with LL DMA driver, refer to
2225 * @note For devices with several ADC: in multimode, some devices
2237 * (1) Available on devices with several ADC instances.
2286 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2366 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2418 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2459 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2522 * or differential (for devices with differential mode available).
2526 * @note For devices with differential mode available:
2563 * or differential (for devices with differential mode available).
2566 * @note For devices with differential mode available:
2581 /* Retrieve bits with position in register depending on parameter */ in LL_ADC_GetCalibrationOffsetFactor()
2583 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ in LL_ADC_GetCalibrationOffsetFactor()
2707 * - It is not recommended to use with interruption or DMA
2713 * - Do use with polling: 1. Start conversion,
2722 * (with startup time between trigger and start of sampling).
2723 * This feature can be combined with low power mode "auto wait".
2724 * @note With ADC low power mode "auto wait", the ADC conversion data read
2763 * - It is not recommended to use with interruption or DMA
2769 * - Do use with polling: 1. Start conversion,
2778 * (with startup time between trigger and start of sampling).
2779 * This feature can be combined with low power mode "auto wait".
2780 * @note With ADC low power mode "auto wait", the ADC conversion data read
2811 * with the lowest value is considered for the subtraction.
2888 * with parts of literals LL_ADC_CHANNEL_x or using
2893 * process the returned value with the helper macro
2939 * comparison with internal channel parameter to be done
3076 * (default setting for compatibility with some ADC on other
3163 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
3224 * - For devices with sequencer fully configurable
3234 * - For devices with sequencer not fully configurable
3283 * - For devices with sequencer fully configurable
3293 * - For devices with sequencer not fully configurable
3478 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
3480 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
3502 * with parts of literals LL_ADC_CHANNEL_x or using
3507 * process the returned value with the helper macro
3575 * comparison with internal channel parameter to be done
3674 * @note Compatibility with devices without feature overrun:
3678 * Therefore, for compatibility with all devices, parameter
3724 * (default setting for compatibility with some ADC on other
3732 * ADC must not be disabled. Can be enabled with or without conversion
3811 /* to match with triggers literals definition. */ in LL_ADC_INJ_GetTriggerSource()
3839 * ADC must not be disabled. Can be enabled with or without conversion
3879 * ADC must not be disabled. Can be enabled with or without conversion
3962 * ADC must not be disabled. Can be enabled with or without conversion
4009 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_INJ_SetSequencerRanks()
4011 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_INJ_SetSequencerRanks()
4027 * with parts of literals LL_ADC_CHANNEL_x or using
4032 * process the returned value with the helper macro
4076 * comparison with internal channel parameter to be done
4091 * updated after one ADC conversion trigger and with data
4099 * ADC group injected automatic trigger is compliant only with
4222 * ADC must not be disabled. Can be enabled with or without conversion
4400 /* Set bits with content of parameter "Rankx_Channel" with bits position */ in LL_ADC_INJ_ConfigQueueContext()
4402 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ in LL_ADC_INJ_ConfigQueueContext()
4523 /* Set bits with content of parameter "SamplingTime" with bits position */ in LL_ADC_SetChannelSamplingTime()
4525 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
4726 * with analog watchdog from sequencer channel definition,
4854 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ in LL_ADC_SetAnalogWDMonitChannels()
4856 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ in LL_ADC_SetAnalogWDMonitChannels()
4872 * with parts of literals LL_ADC_CHANNEL_x or using
4877 * process the returned value with the helper macro
5103 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_SetAnalogWDThresholds()
5106 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_SetAnalogWDThresholds()
5117 * threshold low or raw data with ADC thresholds high and low
5371 * or multimode (for devices with several ADC instances).
5378 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5402 * or multimode (for devices with several ADC instances).
5428 * each ADC uses its own DMA channel, with its individual
5436 * This ADC mode is intended to be used with DMA mode non-circular.
5440 * This ADC mode is intended to be used with DMA mode circular.
5450 * is a raw data with ADC master and slave concatenated.
5476 * each ADC uses its own DMA channel, with its individual
5484 * This ADC mode is intended to be used with DMA mode non-circular.
5488 * This ADC mode is intended to be used with DMA mode circular.
5498 * is a raw data with ADC master and slave concatenated.
5525 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5610 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableDeepPowerDown()
5612 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableDeepPowerDown()
5633 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_DisableDeepPowerDown()
5635 /* to not interfere with bits with HW property "rs". */ in LL_ADC_DisableDeepPowerDown()
5666 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableInternalRegulator()
5668 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableInternalRegulator()
5717 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Enable()
5719 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Enable()
5737 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Disable()
5739 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Disable()
5772 * or differential (for devices with differential mode available).
5779 * @note For devices with differential mode available:
5805 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StartCalibration()
5807 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StartCalibration()
5852 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StartConversion()
5854 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StartConversion()
5864 * ADC must be enabled with conversion on going on group regular,
5872 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StopConversion()
5874 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StopConversion()
5906 * with feature oversampling).
5919 * @note For devices with feature oversampling: Oversampling
5934 * @note For devices with feature oversampling: Oversampling
5949 * @note For devices with feature oversampling: Oversampling
5964 * @note For devices with feature oversampling: Oversampling
5979 * @note For devices with feature oversampling: Oversampling
5993 * or raw data with ADC master and slave concatenated.
5994 * @note If raw data with ADC master and slave concatenated is retrieved,
6049 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StartConversion()
6051 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StartConversion()
6061 * ADC must be enabled with conversion on going on group injected,
6069 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StopConversion()
6071 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StopConversion()
6103 * with feature oversampling).
6128 * @note For devices with feature oversampling: Oversampling
6155 * @note For devices with feature oversampling: Oversampling
6182 * @note For devices with feature oversampling: Oversampling
6209 * @note For devices with feature oversampling: Oversampling
6236 * @note For devices with feature oversampling: Oversampling