177 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Init()  argument
185   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Init()
205   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
254   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FMC_NORSRAM_Init()
259     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
265     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));  in FMC_NORSRAM_Init()
275     MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime));  in FMC_NORSRAM_Init()
281         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_Init()
285         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_Init()
289         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_Init()
293         SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_Init()
308 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_DeInit()  argument
312   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_DeInit()
317   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
323     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
328     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
331   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
338       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);  in FMC_NORSRAM_DeInit()
342       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);  in FMC_NORSRAM_DeInit()
346       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);  in FMC_NORSRAM_DeInit()
350       CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);  in FMC_NORSRAM_DeInit()
365 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Timing_Init()  argument
371   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Timing_Init()
383 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                     …  in FMC_NORSRAM_Timing_Init()
393   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))  in FMC_NORSRAM_Timing_Init()
395     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));  in FMC_NORSRAM_Timing_Init()
397     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);  in FMC_NORSRAM_Timing_Init()
415 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,  in FMC_NORSRAM_Extended_Timing_Init()  argument
426     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  in FMC_NORSRAM_Extended_Timing_Init()
436 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
445     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
475 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
478   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Enable()
482   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
493 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
496   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Disable()
500   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
565 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)  in FMC_NAND_Init()  argument
568   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_Init()
578   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |  in FMC_NAND_Init()
597 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_CommonSpace_Timing_Init()  argument
601   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_CommonSpace_Timing_Init()
612   MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime                                 |  in FMC_NAND_CommonSpace_Timing_Init()
628 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_AttributeSpace_Timing_Init()  argument
632   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_AttributeSpace_Timing_Init()
643   MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime                                 |  in FMC_NAND_AttributeSpace_Timing_Init()
657 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
660   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_DeInit()
664   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
671   WRITE_REG(Device->PCR,  0x00000018U);  in FMC_NAND_DeInit()
672   WRITE_REG(Device->SR,   0x00000040U);  in FMC_NAND_DeInit()
673   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
674   WRITE_REG(Device->PATT, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
705 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
708   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Enable()
715   SET_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Enable()
727 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
730   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Disable()
737   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Disable()
750 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
756   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_GetECC()
763   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
779   *ECCval = (uint32_t)Device->ECCR;  in FMC_NAND_GetECC()