Lines Matching full:with
14 * If no LICENSE file comes with this software, it is provided AS-IS.
116 …_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other S…
119 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
127 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
144 …_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other S…
147 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
155 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
340 …RT | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": S…
346 … (3000UL) /* Analog voltage reference (Vref+) value with which temperature s…
352 … (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature s…
407 …de configuration to operate in independent mode or multimode (for devices with several ADC instanc…
438 * (setting possible with ADC enabled without conversion on going,
439 * ADC enabled with conversion on going, ...)
440 * Each feature can be updated afterwards with a unitary function
441 * and potentially with ADC in a different state than disabled,
469 * (functions with prefix "REG").
476 * (setting possible with ADC enabled without conversion on going,
477 * ADC enabled with conversion on going, ...)
478 * Each feature can be updated afterwards with a unitary function
479 * and potentially with ADC in a different state than disabled,
488 …(default setting for compatibility with some ADC on other STM32 families having this setting set b…
529 * (functions with prefix "INJ").
536 * (setting possible with ADC enabled without conversion on going,
537 * ADC enabled with conversion on going, ...)
538 * Each feature can be updated afterwards with a unitary function
539 * and potentially with ADC in a different state than disabled,
548 …(default setting for compatibility with some ADC on other STM32 families having this setting set b…
584 * @brief Flags defines which can be used with LL_ADC_ReadReg function
627 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
645 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
648 /* List of ADC registers intended to be used (most commonly) with */
651 …egular conversion data register (corresponding to register DR) to be used with ADC configured in i…
653 … (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 d…
663 … ) /*!< ADC synchronous clock derived from AHB clock with prescaler division …
664 …MODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division …
666 …_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
667 …_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division …
668 …_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
669 …_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division …
670 …_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
671 …_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division …
672 …_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
673 …_PRESC_3) /*!< ADC asynchronous clock with prescaler division …
674 …_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
675 …_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division …
676 …_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
721 …en necessary (when previous ADC conversion data is read). See description with function @ref LL_AD…
960 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
961 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
971 …ycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling …
990 … ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequ…
991 … ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequ…
992 … ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequ…
993 …_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequ…
994 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequ…
995 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequ…
996 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequ…
997 … ) /*!< ADC group regular sequencer enable with 9 ranks in the sequ…
998 … | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the seq…
999 … | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the seq…
1000 … | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the seq…
1001 …_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the seq…
1002 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the seq…
1003 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the seq…
1004 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the seq…
1013 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1014 …_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interrupti…
1015 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1016 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1017 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1018 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1019 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1020 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1172 …njected conversion trigger from ADC group regular. Setting compliant only with group injected trig…
1191 … ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequ…
1192 … (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequ…
1193 … (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequ…
1202 …_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interrupti…
1439 … /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (…
1450 …ar conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA …
1451 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
1452 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
1453 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
1454 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
1593 * number is returned, either defined with number
1594 * or with bitfield (only one bit must be set).
1700 * comparison with internal channel parameter to be done
1733 * number in ADC registers. The differentiation is made only with
1873 * number in ADC registers. The differentiation is made only with
2017 * define a single channel to monitor with analog watchdog
2019 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2067 * comparison with internal channel parameter to be done
2193 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2195 * Example, with a ADC resolution of 8 bits, to set the value of
2216 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2217 * Example, with a ADC resolution of 8 bits, to get the value of
2237 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2250 * @brief Helper macro to set the ADC calibration value with both single ended
2252 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2268 * or ADC slave from raw value with both ADC conversion data concatenated.
2271 * In this case the transferred data need to processed with this macro
2288 * @note In case of device with multimode available and a mix of
2289 * ADC instances compliant and not compliant with multimode feature,
2290 * ADC instances not compliant with multimode feature are
2325 * - Multimode (for devices with several ADC instances)
2347 * @note This check is required by functions with setting conditioned to
2351 * @note On devices with only 1 ADC common instance, parameter of this macro
2353 * with devices featuring several ADC common instances).
2465 * On devices with small package, the pin Vref+ is not present
2499 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2557 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2564 * of the current device has characteristics in line with
2634 * intended to be used (most commonly) with DMA transfer.
2638 * @note This macro is intended to be used with LL DMA driver, refer to
2646 * @note For devices with several ADC: in multimode, some devices
2658 * (1) Available on devices with several ADC instances.
2707 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2892 * or differential (for devices with differential mode available).
2896 * @note For devices with differential mode available:
2930 * or differential (for devices with differential mode available).
2933 * @note For devices with differential mode available:
2946 /* Retrieve bits with position in register depending on parameter */ in LL_ADC_GetCalibrationFactor()
2948 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ in LL_ADC_GetCalibrationFactor()
3046 * - It is not recommended to use with interruption or DMA
3052 * - Do use with polling: 1. Start conversion,
3061 * (with startup time between trigger and start of sampling).
3062 * This feature can be combined with low power mode "auto wait".
3063 * @note With ADC low power mode "auto wait", the ADC conversion data read
3102 * - It is not recommended to use with interruption or DMA
3108 * - Do use with polling: 1. Start conversion,
3117 * (with startup time between trigger and start of sampling).
3118 * This feature can be combined with low power mode "auto wait".
3119 * @note With ADC low power mode "auto wait", the ADC conversion data read
3150 * with the lowest value is considered for the subtraction.
3238 * with parts of literals LL_ADC_CHANNEL_x or using
3243 * process the returned value with the helper macro
3300 * comparison with internal channel parameter to be done
3522 * 1 -> 16393 Gain compensation will be enabled with specified value
3538 * 1 -> 16393 Gain compensation is enabled with returned value
3594 * (default setting for compatibility with some ADC on other
3729 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
3828 * - For devices with sequencer fully configurable
3838 * - For devices with sequencer not fully configurable
3887 * - For devices with sequencer fully configurable
3897 * - For devices with sequencer not fully configurable
4093 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
4095 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
4117 * with parts of literals LL_ADC_CHANNEL_x or using
4122 * process the returned value with the helper macro
4201 * comparison with internal channel parameter to be done
4263 * This ADC mode is intended to be used with DMA mode non-circular.
4267 * This ADC mode is intended to be used with DMA mode circular.
4273 * @note For devices with several ADC instances: ADC multimode DMA
4303 * This ADC mode is intended to be used with DMA mode non-circular.
4307 * This ADC mode is intended to be used with DMA mode circular.
4313 * @note For devices with several ADC instances: ADC multimode DMA
4333 * @note Compatibility with devices without feature overrun:
4337 * Therefore, for compatibility with all devices, parameter
4383 * (default setting for compatibility with some ADC on other
4391 * ADC must not be disabled. Can be enabled with or without conversion
4516 /* to match with triggers literals definition. */ in LL_ADC_INJ_GetTriggerSource()
4544 * ADC must not be disabled. Can be enabled with or without conversion
4584 * ADC must not be disabled. Can be enabled with or without conversion
4667 * ADC must not be disabled. Can be enabled with or without conversion
4725 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_INJ_SetSequencerRanks()
4727 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_INJ_SetSequencerRanks()
4743 * with parts of literals LL_ADC_CHANNEL_x or using
4748 * process the returned value with the helper macro
4803 * comparison with internal channel parameter to be done
4818 * updated after one ADC conversion trigger and with data
4826 * ADC group injected automatic trigger is compliant only with
4949 * ADC must not be disabled. Can be enabled with or without conversion
5194 /* Set bits with content of parameter "Rankx_Channel" with bits position */ in LL_ADC_INJ_ConfigQueueContext()
5196 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ in LL_ADC_INJ_ConfigQueueContext()
5332 /* Set bits with content of parameter "SamplingTime" with bits position */ in LL_ADC_SetChannelSamplingTime()
5334 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
5580 * with analog watchdog from sequencer channel definition,
5727 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ in LL_ADC_SetAnalogWDMonitChannels()
5729 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ in LL_ADC_SetAnalogWDMonitChannels()
5745 * with parts of literals LL_ADC_CHANNEL_x or using
5750 * process the returned value with the helper macro
5968 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ in LL_ADC_ConfigAnalogWDThresholds()
5971 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ in LL_ADC_ConfigAnalogWDThresholds()
6015 * ADC can be disabled, enabled with or without conversion on going
6037 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_SetAnalogWDThresholds()
6040 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_SetAnalogWDThresholds()
6052 * threshold low or raw data with ADC thresholds high and low
6054 * @note If raw data with ADC thresholds high and low is retrieved,
6344 * or multimode (for devices with several ADC instances).
6351 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6375 * or multimode (for devices with several ADC instances).
6401 * each ADC uses its own DMA channel, with its individual
6409 * This ADC mode is intended to be used with DMA mode non-circular.
6413 * This ADC mode is intended to be used with DMA mode circular.
6423 * is a raw data with ADC master and slave concatenated.
6452 * each ADC uses its own DMA channel, with its individual
6460 * This ADC mode is intended to be used with DMA mode non-circular.
6464 * This ADC mode is intended to be used with DMA mode circular.
6474 * is a raw data with ADC master and slave concatenated.
6504 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6585 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableDeepPowerDown()
6587 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableDeepPowerDown()
6608 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_DisableDeepPowerDown()
6610 /* to not interfere with bits with HW property "rs". */ in LL_ADC_DisableDeepPowerDown()
6641 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableInternalRegulator()
6643 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableInternalRegulator()
6692 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Enable()
6694 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Enable()
6712 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Disable()
6714 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Disable()
6747 * or differential (for devices with differential mode available).
6751 * @note For devices with differential mode available:
6770 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StartCalibration()
6772 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StartCalibration()
6817 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StartConversion()
6819 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StartConversion()
6829 * ADC must be enabled with conversion on going on group regular,
6837 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StopConversion()
6839 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StopConversion()
6913 * with feature oversampling).
6926 * @note For devices with feature oversampling: Oversampling
6941 * @note For devices with feature oversampling: Oversampling
6956 * @note For devices with feature oversampling: Oversampling
6971 * @note For devices with feature oversampling: Oversampling
6986 * or raw data with ADC master and slave concatenated.
6987 * @note If raw data with ADC master and slave concatenated is retrieved,
7042 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StartConversion()
7044 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StartConversion()
7054 * ADC must be enabled with conversion on going on group injected,
7062 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StopConversion()
7064 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StopConversion()
7096 * with feature oversampling).
7121 * @note For devices with feature oversampling: Oversampling
7148 * @note For devices with feature oversampling: Oversampling
7175 * @note For devices with feature oversampling: Oversampling
7202 * @note For devices with feature oversampling: Oversampling