Lines Matching refs:Device
238 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
246 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
271 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
332 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
338 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
346 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
360 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
364 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
369 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
375 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
380 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
383 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
397 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Timing_Init() argument
405 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Timing_Init()
416 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
426 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
428 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
430 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
449 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, in FMC_NORSRAM_Extended_Timing_Init() argument
460 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); in FMC_NORSRAM_Extended_Timing_Init()
469 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
477 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
507 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Enable() argument
510 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Enable()
514 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
525 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Disable() argument
528 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Disable()
532 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Disable()
597 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
600 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_Init()
614 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
625 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
635 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
655 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_CommonSpace_Timing_Init() argument
659 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_CommonSpace_Timing_Init()
671 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_CommonSpace_Timing_Init()
679 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_CommonSpace_Timing_Init()
689 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
706 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_AttributeSpace_Timing_Init() argument
710 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_AttributeSpace_Timing_Init()
722 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_AttributeSpace_Timing_Init()
730 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime … in FMC_NAND_AttributeSpace_Timing_Init()
740 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
755 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_DeInit() argument
758 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_DeInit()
762 __FMC_NAND_DISABLE(Device, Bank); in FMC_NAND_DeInit()
769 WRITE_REG(Device->PCR2, 0x00000018U); in FMC_NAND_DeInit()
770 WRITE_REG(Device->SR2, 0x00000040U); in FMC_NAND_DeInit()
771 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); in FMC_NAND_DeInit()
772 WRITE_REG(Device->PATT2, 0xFCFCFCFCU); in FMC_NAND_DeInit()
778 WRITE_REG(Device->PCR3, 0x00000018U); in FMC_NAND_DeInit()
779 WRITE_REG(Device->SR3, 0x00000040U); in FMC_NAND_DeInit()
780 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); in FMC_NAND_DeInit()
781 WRITE_REG(Device->PATT3, 0xFCFCFCFCU); in FMC_NAND_DeInit()
788 WRITE_REG(Device->PCR, 0x00000018U); in FMC_NAND_DeInit()
789 WRITE_REG(Device->SR, 0x00000040U); in FMC_NAND_DeInit()
790 WRITE_REG(Device->PMEM, 0xFCFCFCFCU); in FMC_NAND_DeInit()
791 WRITE_REG(Device->PATT, 0xFCFCFCFCU); in FMC_NAND_DeInit()
823 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Enable() argument
826 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Enable()
833 SET_BIT(Device->PCR2, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Enable()
837 SET_BIT(Device->PCR3, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Enable()
843 SET_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Enable()
856 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Disable() argument
859 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Disable()
866 CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Disable()
870 CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN); in FMC_NAND_ECC_Disable()
876 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Disable()
890 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, in FMC_NAND_GetECC() argument
896 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_GetECC()
903 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) in FMC_NAND_GetECC()
919 *ECCval = (uint32_t)Device->ECCR2; in FMC_NAND_GetECC()
924 *ECCval = (uint32_t)Device->ECCR3; in FMC_NAND_GetECC()
931 *ECCval = (uint32_t)Device->ECCR; in FMC_NAND_GetECC()
991 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) in FMC_PCCARD_Init() argument
994 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_Init()
1002 MODIFY_REG(Device->PCR4, in FMC_PCCARD_Init()
1024 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, in FMC_PCCARD_CommonSpace_Timing_Init() argument
1028 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_CommonSpace_Timing_Init()
1037 MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK, in FMC_PCCARD_CommonSpace_Timing_Init()
1053 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, in FMC_PCCARD_AttributeSpace_Timing_Init() argument
1057 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_AttributeSpace_Timing_Init()
1066 MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK, in FMC_PCCARD_AttributeSpace_Timing_Init()
1082 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, in FMC_PCCARD_IOSpace_Timing_Init() argument
1086 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_IOSpace_Timing_Init()
1095 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, in FMC_PCCARD_IOSpace_Timing_Init()
1109 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) in FMC_PCCARD_DeInit() argument
1112 assert_param(IS_FMC_PCCARD_DEVICE(Device)); in FMC_PCCARD_DeInit()
1115 __FMC_PCCARD_DISABLE(Device); in FMC_PCCARD_DeInit()
1118 Device->PCR4 = 0x00000018U; in FMC_PCCARD_DeInit()
1119 Device->SR4 = 0x00000040U; in FMC_PCCARD_DeInit()
1120 Device->PMEM4 = 0xFCFCFCFCU; in FMC_PCCARD_DeInit()
1121 Device->PATT4 = 0xFCFCFCFCU; in FMC_PCCARD_DeInit()
1122 Device->PIO4 = 0xFCFCFCFCU; in FMC_PCCARD_DeInit()
1180 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
1183 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Init()
1198 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
1212 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
1220 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
1242 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_Timing_Init() argument
1246 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Timing_Init()
1259 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
1271 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
1277 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
1294 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_DeInit() argument
1297 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_DeInit()
1301 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
1302 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
1303 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
1304 Device->SDRTR = 0x00000000U; in FMC_SDRAM_DeInit()
1305 Device->SDSR = 0x00000000U; in FMC_SDRAM_DeInit()
1335 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Enable() argument
1338 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Enable()
1342 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
1352 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Disable() argument
1355 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Disable()
1359 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
1372 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SendCommand() argument
1377 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SendCommand()
1384 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1392 while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) in FMC_SDRAM_SendCommand()
1412 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) in FMC_SDRAM_ProgramRefreshRate() argument
1415 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_ProgramRefreshRate()
1419 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); in FMC_SDRAM_ProgramRefreshRate()
1430 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SetAutoRefreshNumber() argument
1434 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SetAutoRefreshNumber()
1438 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
1452 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_GetModeStatus() argument
1457 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_GetModeStatus()
1463 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); in FMC_SDRAM_GetModeStatus()
1467 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); in FMC_SDRAM_GetModeStatus()