Lines Matching full:with
14 * If no LICENSE file comes with this software, it is provided AS-IS.
123 …_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other S…
126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
164 …_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other S…
167 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
175 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
362 …RT | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": S…
368 …32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature s…
374 …_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature s…
388 * @brief Driver macro reserved for internal use: isolate bits with the
441 …de configuration to operate in independent mode or multimode (for devices with several ADC instanc…
472 * (setting possible with ADC enabled without conversion on going,
473 * ADC enabled with conversion on going, ...)
474 * Each feature can be updated afterwards with a unitary function
475 * and potentially with ADC in a different state than disabled,
503 * (functions with prefix "REG").
510 * (setting possible with ADC enabled without conversion on going,
511 * ADC enabled with conversion on going, ...)
512 * Each feature can be updated afterwards with a unitary function
513 * and potentially with ADC in a different state than disabled,
522 …(default setting for compatibility with some ADC on other STM32 families having this setting set b…
563 * (functions with prefix "INJ").
570 * (setting possible with ADC enabled without conversion on going,
571 * ADC enabled with conversion on going, ...)
572 * Each feature can be updated afterwards with a unitary function
573 * and potentially with ADC in a different state than disabled,
582 …(default setting for compatibility with some ADC on other STM32 families having this setting set b…
618 * @brief Flags defines which can be used with LL_ADC_ReadReg function
661 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
679 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
682 /* List of ADC registers intended to be used (most commonly) with */
685 …egular conversion data register (corresponding to register DR) to be used with ADC configured in i…
687 … (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 d…
697 … ) /*!< ADC synchronous clock derived from AHB clock with prescaler division …
698 …MODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division …
744 …en necessary (when previous ADC conversion data is read). See description with function @ref LL_AD…
971 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
972 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
990 … ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequ…
991 … ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequ…
992 … ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequ…
993 …_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequ…
994 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequ…
995 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequ…
996 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequ…
997 … ) /*!< ADC group regular sequencer enable with 9 ranks in the sequ…
998 … | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the seq…
999 … | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the seq…
1000 … | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the seq…
1001 …_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the seq…
1002 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the seq…
1003 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the seq…
1004 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the seq…
1013 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1014 …_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interrupti…
1015 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1016 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1017 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1018 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1019 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1020 …C_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
1186 …njected conversion trigger from ADC group regular. Setting compliant only with group injected trig…
1204 … ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequ…
1205 … (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequ…
1206 … (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequ…
1215 …_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interrupti…
1381 … /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (…
1392 …ar conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA …
1393 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
1394 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
1395 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
1396 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
1535 * number is returned, either defined with number
1536 * or with bitfield (only one bit must be set).
1626 * comparison with internal channel parameter to be done
1659 * number in ADC registers. The differentiation is made only with
1783 * number in ADC registers. The differentiation is made only with
1909 * define a single channel to monitor with analog watchdog
1911 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1951 * comparison with internal channel parameter to be done
2063 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2065 * Example, with a ADC resolution of 8 bits, to set the value of
2086 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2087 * Example, with a ADC resolution of 8 bits, to get the value of
2107 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2120 * @brief Helper macro to set the ADC calibration value with both single ended
2122 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2138 * or ADC slave from raw value with both ADC conversion data concatenated.
2141 * In this case the transferred data need to processed with this macro
2158 * - Multimode (for devices with several ADC instances)
2185 * @note This check is required by functions with setting conditioned to
2189 * @note On devices with only 1 ADC common instance, parameter of this macro
2191 * with devices featuring several ADC common instances).
2294 * On devices with small package, the pin Vref+ is not present
2328 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2386 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2393 * of the current device has characteristics in line with
2464 * intended to be used (most commonly) with DMA transfer.
2468 * @note This macro is intended to be used with LL DMA driver, refer to
2476 * @note For devices with several ADC: in multimode, some devices
2488 * (1) Available on devices with several ADC instances.
2537 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2593 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2645 * or differential (for devices with differential mode available).
2649 * @note For devices with differential mode available:
2683 * or differential (for devices with differential mode available).
2686 * @note For devices with differential mode available:
2699 /* Retrieve bits with position in register depending on parameter */ in LL_ADC_GetCalibrationFactor()
2701 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ in LL_ADC_GetCalibrationFactor()
2797 * - It is not recommended to use with interruption or DMA
2803 * - Do use with polling: 1. Start conversion,
2812 * (with startup time between trigger and start of sampling).
2813 * This feature can be combined with low power mode "auto wait".
2814 * @note With ADC low power mode "auto wait", the ADC conversion data read
2853 * - It is not recommended to use with interruption or DMA
2859 * - Do use with polling: 1. Start conversion,
2868 * (with startup time between trigger and start of sampling).
2869 * This feature can be combined with low power mode "auto wait".
2870 * @note With ADC low power mode "auto wait", the ADC conversion data read
2901 * with the lowest value is considered for the subtraction.
2979 * with parts of literals LL_ADC_CHANNEL_x or using
2984 * process the returned value with the helper macro
3031 * comparison with internal channel parameter to be done
3141 * (default setting for compatibility with some ADC on other
3302 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
3364 * - For devices with sequencer fully configurable
3374 * - For devices with sequencer not fully configurable
3423 * - For devices with sequencer fully configurable
3433 * - For devices with sequencer not fully configurable
3621 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
3623 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
3645 * with parts of literals LL_ADC_CHANNEL_x or using
3650 * process the returned value with the helper macro
3721 * comparison with internal channel parameter to be done
3783 * This ADC mode is intended to be used with DMA mode non-circular.
3787 * This ADC mode is intended to be used with DMA mode circular.
3793 * @note For devices with several ADC instances: ADC multimode DMA
3823 * This ADC mode is intended to be used with DMA mode non-circular.
3827 * This ADC mode is intended to be used with DMA mode circular.
3833 * @note For devices with several ADC instances: ADC multimode DMA
3853 * @note Compatibility with devices without feature overrun:
3857 * Therefore, for compatibility with all devices, parameter
3903 * (default setting for compatibility with some ADC on other
3918 * ADC must not be disabled. Can be enabled with or without conversion
4057 /* to match with triggers literals definition. */ in LL_ADC_INJ_GetTriggerSource()
4085 * ADC must not be disabled. Can be enabled with or without conversion
4132 * ADC must not be disabled. Can be enabled with or without conversion
4220 * ADC must not be disabled. Can be enabled with or without conversion
4270 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_INJ_SetSequencerRanks()
4272 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_INJ_SetSequencerRanks()
4288 * with parts of literals LL_ADC_CHANNEL_x or using
4293 * process the returned value with the helper macro
4340 * comparison with internal channel parameter to be done
4355 * updated after one ADC conversion trigger and with data
4363 * ADC group injected automatic trigger is compliant only with
4480 * ADC must not be disabled. Can be enabled with or without conversion
4700 /* Set bits with content of parameter "Rankx_Channel" with bits position */ in LL_ADC_INJ_ConfigQueueContext()
4702 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ in LL_ADC_INJ_ConfigQueueContext()
4825 /* Set bits with content of parameter "SamplingTime" with bits position */ in LL_ADC_SetChannelSamplingTime()
4827 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
5048 * with analog watchdog from sequencer channel definition,
5181 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ in LL_ADC_SetAnalogWDMonitChannels()
5183 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ in LL_ADC_SetAnalogWDMonitChannels()
5199 * with parts of literals LL_ADC_CHANNEL_x or using
5204 * process the returned value with the helper macro
5326 /* - channel ID with number */ in LL_ADC_GetAnalogWDMonitChannels()
5327 /* - channel ID with bitfield */ in LL_ADC_GetAnalogWDMonitChannels()
5342 /* - channel ID with number */ in LL_ADC_GetAnalogWDMonitChannels()
5343 /* - channel ID with bitfield */ in LL_ADC_GetAnalogWDMonitChannels()
5414 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ in LL_ADC_ConfigAnalogWDThresholds()
5417 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ in LL_ADC_ConfigAnalogWDThresholds()
5478 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_SetAnalogWDThresholds()
5481 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_SetAnalogWDThresholds()
5492 * threshold low or raw data with ADC thresholds high and low
5494 * @note If raw data with ADC thresholds high and low is retrieved,
5539 * or multimode (for devices with several ADC instances).
5546 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5570 * or multimode (for devices with several ADC instances).
5596 * each ADC uses its own DMA channel, with its individual
5604 * This ADC mode is intended to be used with DMA mode non-circular.
5608 * This ADC mode is intended to be used with DMA mode circular.
5618 * is a raw data with ADC master and slave concatenated.
5647 * each ADC uses its own DMA channel, with its individual
5655 * This ADC mode is intended to be used with DMA mode non-circular.
5659 * This ADC mode is intended to be used with DMA mode circular.
5669 * is a raw data with ADC master and slave concatenated.
5699 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5786 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableInternalRegulator()
5788 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableInternalRegulator()
5837 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Enable()
5839 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Enable()
5857 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Disable()
5859 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Disable()
5892 * or differential (for devices with differential mode available).
5896 * @note For devices with differential mode available:
5915 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StartCalibration()
5917 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StartCalibration()
5962 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StartConversion()
5964 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StartConversion()
5974 * ADC must be enabled with conversion on going on group regular,
5982 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StopConversion()
5984 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StopConversion()
6016 * with feature oversampling).
6029 * @note For devices with feature oversampling: Oversampling
6044 * @note For devices with feature oversampling: Oversampling
6059 * @note For devices with feature oversampling: Oversampling
6074 * @note For devices with feature oversampling: Oversampling
6089 * or raw data with ADC master and slave concatenated.
6090 * @note If raw data with ADC master and slave concatenated is retrieved,
6145 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StartConversion()
6147 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StartConversion()
6157 * ADC must be enabled with conversion on going on group injected,
6165 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StopConversion()
6167 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StopConversion()
6199 * with feature oversampling).
6224 * @note For devices with feature oversampling: Oversampling
6251 * @note For devices with feature oversampling: Oversampling
6278 * @note For devices with feature oversampling: Oversampling
6305 * @note For devices with feature oversampling: Oversampling
7464 …32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature s…
7470 …_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature s…
7484 * @brief Driver macro reserved for internal use: isolate bits with the
7529 * (setting possible with ADC enabled without conversion on going,
7530 * ADC enabled with conversion on going, ...)
7531 * Each feature can be updated afterwards with a unitary function
7532 * and potentially with ADC in a different state than disabled,
7555 * (functions with prefix "REG").
7562 * (setting possible with ADC enabled without conversion on going,
7563 * ADC enabled with conversion on going, ...)
7564 * Each feature can be updated afterwards with a unitary function
7565 * and potentially with ADC in a different state than disabled,
7573 … @note On this STM32 series, external trigger is set with trigger polarity: rising edge
7609 * (functions with prefix "INJ").
7616 * (setting possible with ADC enabled without conversion on going,
7617 * ADC enabled with conversion on going, ...)
7618 * Each feature can be updated afterwards with a unitary function
7619 * and potentially with ADC in a different state than disabled,
7627 … @note On this STM32 series, external trigger is set with trigger polarity: rising edge
7664 * @brief Flags defines which can be used with LL_ADC_ReadReg function
7677 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
7687 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
7690 /* List of ADC registers intended to be used (most commonly) with */
7693 …egular conversion data register (corresponding to register DR) to be used with ADC configured in i…
7812 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
7821 … ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequ…
7822 … ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequ…
7823 … ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequ…
7824 …_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequ…
7825 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequ…
7826 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequ…
7827 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequ…
7828 … ) /*!< ADC group regular sequencer enable with 9 ranks in the sequ…
7829 … | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the seq…
7830 … | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the seq…
7831 … | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the seq…
7832 …_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the seq…
7833 …_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the seq…
7834 …_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the seq…
7835 …_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the seq…
7844 …DC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
7845 …C_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interrupti…
7846 …DC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
7847 …DC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
7848 …DC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
7849 …DC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
7850 …DC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
7851 …DC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
7906 …njected conversion trigger from ADC group regular. Setting compliant only with group injected trig…
7916 … ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequ…
7917 … (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequ…
7918 … (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequ…
7927 …JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interrupti…
8135 * number is returned, either defined with number
8136 * or with bitfield (only one bit must be set).
8196 * comparison with internal channel parameter to be done
8227 * number in ADC registers. The differentiation is made only with
8328 * number in ADC registers. The differentiation is made only with
8351 * define a single channel to monitor with analog watchdog
8353 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
8382 * comparison with internal channel parameter to be done
8470 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
8471 * Example, with a ADC resolution of 8 bits, to set the value of
8483 /* This macro has been kept anyway for compatibility with other */
8492 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
8493 * Example, with a ADC resolution of 8 bits, to get the value of
8505 /* This macro has been kept anyway for compatibility with other */
8515 * - Multimode (for devices with several ADC instances)
8519 * (equivalence with other STM32 families featuring several
8530 * @note This check is required by functions with setting conditioned to
8534 * @note On devices with only 1 ADC common instance, parameter of this macro
8536 * with devices featuring several ADC common instances).
8539 * (equivalence with other STM32 families featuring several
8616 * On devices with small package, the pin Vref+ is not present
8648 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
8704 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
8711 * of the current device has characteristics in line with
8779 * intended to be used (most commonly) with DMA transfer.
8783 * @note This macro is intended to be used with LL DMA driver, refer to
8791 * @note For devices with several ADC: in multimode, some devices
8968 * @note On this STM32 series, external trigger is set with trigger polarity:
9043 * - For devices with sequencer fully configurable
9053 * - For devices with sequencer not fully configurable
9104 * - For devices with sequencer fully configurable
9114 * - For devices with sequencer not fully configurable
9289 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
9291 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
9313 * with parts of literals LL_ADC_CHANNEL_x or using
9318 * process the returned value with the helper macro
9378 * comparison with internal channel parameter to be done
9436 * This ADC mode is intended to be used with DMA mode non-circular.
9440 * This ADC mode is intended to be used with DMA mode circular.
9468 * This ADC mode is intended to be used with DMA mode non-circular.
9472 * This ADC mode is intended to be used with DMA mode circular.
9502 * @note On this STM32 series, external trigger is set with trigger polarity:
9707 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_INJ_SetSequencerRanks()
9709 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_INJ_SetSequencerRanks()
9725 * with parts of literals LL_ADC_CHANNEL_x or using
9730 * process the returned value with the helper macro
9766 * comparison with internal channel parameter to be done
9781 * updated after one ADC conversion trigger and with data
9789 * ADC group injected automatic trigger is compliant only with
9965 /* Set bits with content of parameter "SamplingTime" with bits position */ in LL_ADC_SetChannelSamplingTime()
9967 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
10061 * with analog watchdog from sequencer channel definition,
10156 * with parts of literals LL_ADC_CHANNEL_x or using
10161 * process the returned value with the helper macro
10337 * or differential (for devices with differential mode available).
10417 * with feature oversampling).
10430 * @note For devices with feature oversampling: Oversampling
10493 * with feature oversampling).
10518 * @note For devices with feature oversampling: Oversampling