Lines Matching refs:CFGR2
821 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); in LL_RCC_HSE_GetPrediv2()
1183 MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); in LL_RCC_SetI2SClockSource()
1242 return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); in LL_RCC_GetI2SClockSource()
1481 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), in LL_RCC_PLL_ConfigDomain_SYS()
1484 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_ConfigDomain_SYS()
1502 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); in LL_RCC_PLL_SetMainSource()
1522 uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); in LL_RCC_PLL_GetMainSource()
1585 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_GetPrediv()
1665 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); in LL_RCC_PLL_ConfigDomain_PLLI2S()
1684 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); in LL_RCC_PLLI2S_GetMultiplicator()
1762 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator); in LL_RCC_PLL_ConfigDomain_PLL2()
1781 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL)); in LL_RCC_PLL2_GetMultiplicator()