Lines Matching full:with
14 * If no LICENSE file comes with this software, it is provided AS-IS.
71 …_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other S…
74 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
82 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
103 …MBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "f…
254 …TP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": S…
260 … ( 3000UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has b…
266 …(with taking into account conversion from digital value resolution 12 bit, analog voltage referenc…
270 … ( 3000UL) /* Analog voltage reference (Vref+) voltage with which temperature s…
334 * (setting possible with ADC enabled without conversion on going,
335 * ADC enabled with conversion on going, ...)
336 * Each feature can be updated afterwards with a unitary function
337 * and potentially with ADC in a different state than disabled,
346 …ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clo…
374 * (functions with prefix "REG").
381 * (setting possible with ADC enabled without conversion on going,
382 * ADC enabled with conversion on going, ...)
383 * Each feature can be updated afterwards with a unitary function
384 * and potentially with ADC in a different state than disabled,
393 …(default setting for compatibility with some ADC on other STM32 families having this setting set b…
441 * @brief Flags defines which can be used with LL_ADC_ReadReg function
459 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
476 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
479 /* List of ADC registers intended to be used (most commonly) with */
482 …egular conversion data register (corresponding to register DR) to be used with ADC configured in i…
491 …_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
492 …_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division …
493 …_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
494 …_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division …
495 …_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
496 …_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division …
497 …_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
498 …_PRESC_3) /*!< ADC asynchronous clock with prescaler division …
499 …_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
500 …_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division …
501 …_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division …
565 …en necessary (when previous ADC conversion data is read). See description with function @ref LL_AD…
566 …n a new ADC conversion is triggered (with startup time between trigger and start of sampling). See…
567 …DC low power modes auto wait and auto power-off combined. See description with function @ref LL_AD…
667 …mber of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circul…
668 …sferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. …
695 …LE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequ…
696 …LE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequ…
697 …LE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequ…
698 …LE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequ…
699 …LE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequ…
700 …LE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequ…
701 …LE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequ…
709 …ber to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in…
710 …mber to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in…
719 … /*!< ADC group regular sequencer discontinuous mode enable with sequence interrupti…
814 …f ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices…
970 * number is returned, either defined with number
971 * or with bitfield (only one bit must be set).
1005 * comparison with internal channel parameter to be done
1081 * comparison with internal channel parameter to be done
1104 * number in ADC registers. The differentiation is made only with
1139 * comparison with internal channel parameter to be done
1194 * comparison with internal channel parameter to be done
1236 * number in ADC registers. The differentiation is made only with
1255 * define a single channel to monitor with analog watchdog
1257 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1295 * comparison with internal channel parameter to be done
1339 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1341 * Example, with a ADC resolution of 8 bits, to set the value of
1362 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1363 * Example, with a ADC resolution of 8 bits, to get the value of
1383 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1400 * - Multimode (for devices with several ADC instances)
1411 * @note This check is required by functions with setting conditioned to
1415 * @note On devices with only 1 ADC common instance, parameter of this macro
1417 * with devices featuring several ADC common instances).
1501 * On devices with small package, the pin Vref+ is not present
1534 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1541 * of the current device has characteristics in line with
1610 * intended to be used (most commonly) with DMA transfer.
1614 * @note This macro is intended to be used with LL DMA driver, refer to
1622 * @note For devices with several ADC: in multimode, some devices
1654 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1737 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1778 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1806 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1907 * or differential (for devices with differential mode available).
1929 * or differential (for devices with differential mode available).
2029 * - It is not recommended to use with interruption or DMA
2035 * - Do use with polling: 1. Start conversion,
2044 * (with startup time between trigger and start of sampling).
2045 * This feature can be combined with low power mode "auto wait".
2046 * @note With ADC low power mode "auto wait", the ADC conversion data read
2086 * - It is not recommended to use with interruption or DMA
2092 * - Do use with polling: 1. Start conversion,
2101 * (with startup time between trigger and start of sampling).
2102 * This feature can be combined with low power mode "auto wait".
2103 * @note With ADC low power mode "auto wait", the ADC conversion data read
2133 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2263 * (default setting for compatibility with some ADC on other
2323 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
2447 * - For devices with sequencer fully configurable
2457 * - For devices with sequencer not fully configurable
2519 * - For devices with sequencer fully configurable
2529 * - For devices with sequencer not fully configurable
2752 * comparison with internal channel parameter to be done
2759 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
2761 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
2781 * with parts of literals LL_ADC_CHANNEL_x or using
2786 * process the returned value with the helper macro
2839 * comparison with internal channel parameter to be done
2865 * This function can be used with setting "not fully configurable".
2941 * comparison with internal channel parameter to be done
2948 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_REG_SetSequencerChannels()
2966 * This function can be used with setting "not fully configurable".
3042 * comparison with internal channel parameter to be done
3049 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_REG_SetSequencerChAdd()
3067 * This function can be used with setting "not fully configurable".
3143 * comparison with internal channel parameter to be done
3150 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_REG_SetSequencerChRem()
3166 * This function can be used with setting "not fully configurable".
3234 * comparison with internal channel parameter to be done
3316 * This ADC mode is intended to be used with DMA mode non-circular.
3320 * This ADC mode is intended to be used with DMA mode circular.
3353 * This ADC mode is intended to be used with DMA mode non-circular.
3357 * This ADC mode is intended to be used with DMA mode circular.
3381 * @note Compatibility with devices without feature overrun:
3385 * Therefore, for compatibility with all devices, parameter
3500 * comparison with internal channel parameter to be done
3510 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
3579 * comparison with internal channel parameter to be done
3616 * with analog watchdog from sequencer channel definition,
3673 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ in LL_ADC_SetAnalogWDMonitChannels()
3675 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ in LL_ADC_SetAnalogWDMonitChannels()
3699 * with parts of literals LL_ADC_CHANNEL_x or using
3704 * process the returned value with the helper macro
3898 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ in LL_ADC_ConfigAnalogWDThresholds()
3901 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ in LL_ADC_ConfigAnalogWDThresholds()
3953 * ADC can be disabled, enabled with or without conversion on going
3975 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_SetAnalogWDThresholds()
3978 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_SetAnalogWDThresholds()
3989 * threshold low or raw data with ADC thresholds high and low
3991 * @note If raw data with ADC thresholds high and low is retrieved,
4017 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_GetAnalogWDThresholds()
4020 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_GetAnalogWDThresholds()
4219 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableInternalRegulator()
4221 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableInternalRegulator()
4270 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Enable()
4272 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Enable()
4290 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Disable()
4292 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Disable()
4325 * or differential (for devices with differential mode available).
4329 * @note In case of usage of ADC with DMA transfer:
4353 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StartCalibration()
4355 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StartCalibration()
4400 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StartConversion()
4402 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StartConversion()
4412 * ADC must be enabled with conversion on going on group regular,
4420 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StopConversion()
4422 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StopConversion()
4454 * with feature oversampling).
4467 * @note For devices with feature oversampling: Oversampling
4482 * @note For devices with feature oversampling: Oversampling
4497 * @note For devices with feature oversampling: Oversampling
4512 * @note For devices with feature oversampling: Oversampling