Lines Matching refs:Init
239 FMC_NORSRAM_InitTypeDef *Init) in FMC_NORSRAM_Init() argument
247 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
248 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
249 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
250 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
251 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
252 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
254 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); in FMC_NORSRAM_Init()
256 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
257 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
258 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
259 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); in FMC_NORSRAM_Init()
260 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); in FMC_NORSRAM_Init()
261 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); in FMC_NORSRAM_Init()
263 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); in FMC_NORSRAM_Init()
266 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); in FMC_NORSRAM_Init()
268 assert_param(IS_FMC_PAGESIZE(Init->PageSize)); in FMC_NORSRAM_Init()
271 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
274 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) in FMC_NORSRAM_Init()
284 Init->DataAddressMux | \ in FMC_NORSRAM_Init()
285 Init->MemoryType | \ in FMC_NORSRAM_Init()
286 Init->MemoryDataWidth | \ in FMC_NORSRAM_Init()
287 Init->BurstAccessMode | \ in FMC_NORSRAM_Init()
288 Init->WaitSignalPolarity | \ in FMC_NORSRAM_Init()
289 Init->WaitSignalActive | \ in FMC_NORSRAM_Init()
290 Init->WriteOperation | \ in FMC_NORSRAM_Init()
291 Init->WaitSignal | \ in FMC_NORSRAM_Init()
292 Init->ExtendedMode | \ in FMC_NORSRAM_Init()
293 Init->AsynchronousWait | \ in FMC_NORSRAM_Init()
294 Init->WriteBurst); in FMC_NORSRAM_Init()
297 btcr_reg |= Init->WrapMode; in FMC_NORSRAM_Init()
300 btcr_reg |= Init->ContinuousClock; in FMC_NORSRAM_Init()
303 btcr_reg |= Init->WriteFifo; in FMC_NORSRAM_Init()
305 btcr_reg |= Init->PageSize; in FMC_NORSRAM_Init()
332 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
336 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
338 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
343 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
346 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
597 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
601 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); in FMC_NAND_Init()
602 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); in FMC_NAND_Init()
603 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NAND_Init()
604 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); in FMC_NAND_Init()
605 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); in FMC_NAND_Init()
606 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); in FMC_NAND_Init()
607 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); in FMC_NAND_Init()
611 if (Init->NandBank == FMC_NAND_BANK2) in FMC_NAND_Init()
614 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
616 … Init->MemoryDataWidth | in FMC_NAND_Init()
617 … Init->EccComputation | in FMC_NAND_Init()
618 … Init->ECCPageSize | in FMC_NAND_Init()
619 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | in FMC_NAND_Init()
620 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); in FMC_NAND_Init()
625 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
627 … Init->MemoryDataWidth | in FMC_NAND_Init()
628 … Init->EccComputation | in FMC_NAND_Init()
629 … Init->ECCPageSize | in FMC_NAND_Init()
630 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | in FMC_NAND_Init()
631 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); in FMC_NAND_Init()
635 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
637 Init->MemoryDataWidth | in FMC_NAND_Init()
638 Init->EccComputation | in FMC_NAND_Init()
639 Init->ECCPageSize | in FMC_NAND_Init()
640 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | in FMC_NAND_Init()
641 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); in FMC_NAND_Init()
991 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) in FMC_PCCARD_Init() argument
996 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); in FMC_PCCARD_Init()
997 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); in FMC_PCCARD_Init()
998 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); in FMC_PCCARD_Init()
1009 Init->Waitfeature | in FMC_PCCARD_Init()
1011 (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) | in FMC_PCCARD_Init()
1012 (Init->TARSetupTime << FMC_PCR4_TAR_Pos))); in FMC_PCCARD_Init()
1180 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
1184 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); in FMC_SDRAM_Init()
1185 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); in FMC_SDRAM_Init()
1186 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); in FMC_SDRAM_Init()
1187 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_SDRAM_Init()
1188 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); in FMC_SDRAM_Init()
1189 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); in FMC_SDRAM_Init()
1190 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); in FMC_SDRAM_Init()
1191 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); in FMC_SDRAM_Init()
1192 assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); in FMC_SDRAM_Init()
1193 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); in FMC_SDRAM_Init()
1196 if (Init->SDBank == FMC_SDRAM_BANK1) in FMC_SDRAM_Init()
1200 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
1201 Init->RowBitsNumber | in FMC_SDRAM_Init()
1202 Init->MemoryDataWidth | in FMC_SDRAM_Init()
1203 Init->InternalBankNumber | in FMC_SDRAM_Init()
1204 Init->CASLatency | in FMC_SDRAM_Init()
1205 Init->WriteProtection | in FMC_SDRAM_Init()
1206 Init->SDClockPeriod | in FMC_SDRAM_Init()
1207 Init->ReadBurst | in FMC_SDRAM_Init()
1208 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
1216 (Init->SDClockPeriod | in FMC_SDRAM_Init()
1217 Init->ReadBurst | in FMC_SDRAM_Init()
1218 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
1222 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
1223 Init->RowBitsNumber | in FMC_SDRAM_Init()
1224 Init->MemoryDataWidth | in FMC_SDRAM_Init()
1225 Init->InternalBankNumber | in FMC_SDRAM_Init()
1226 Init->CASLatency | in FMC_SDRAM_Init()
1227 Init->WriteProtection)); in FMC_SDRAM_Init()